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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [s3e-500/] [src/] [spi/] [spi.v] - Blame information for rev 230

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//
// spi.v -- SPI bus controller
//
 
 
module spi(clk, reset, spi_en,
           dac_sample_l, dac_sample_r, dac_next,
           spi_sck, spi_mosi,
           dac_cs_n, dac_clr_n,
           amp_cs_n, amp_shdn,
           ad_conv);
    // internal interface
    input clk;
    input reset;
    input spi_en;
    // DAC controller interface
    input [15:0] dac_sample_l;
    input [15:0] dac_sample_r;
    output dac_next;
    // external interface
    output spi_sck;
    output spi_mosi;
    output dac_cs_n;
    output dac_clr_n;
    output amp_cs_n;
    output amp_shdn;
    output ad_conv;
 
  //------------------------------------------------------------
 
  //
  // SPI timing and clock generator
  //
 
  reg [9:0] timing;
 
  always @(posedge clk) begin
    if (reset) begin
      timing <= 10'h0;
    end else begin
      if (spi_en == 1'b0 && timing == 10'h0) begin
        // put SPI on hold in state 0 if disabled
        timing <= timing;
      end else begin
        // else step through the command cycle
        timing <= timing + 1;
      end
    end
  end
 
  assign spi_sck = timing[0];
 
  //------------------------------------------------------------
 
  //
  // DAC controller
  //
 
  reg dac_ld;
  reg [47:0] dac_sr;
  wire dac_shift;
 
  assign dac_next = (timing[9:0] == 10'h001) ? 1 : 0;
 
  always @(posedge clk) begin
    if (reset) begin
      dac_ld <= 1'b1;
    end else begin
      if (timing[9:0] == 10'h001) begin
        dac_ld <= 1'b0;
      end
      if (timing[9:0] == 10'h031) begin
        dac_ld <= 1'b1;
      end
      if (timing[9:0] == 10'h033) begin
        dac_ld <= 1'b0;
      end
      if (timing[9:0] == 10'h063) begin
        dac_ld <= 1'b1;
      end
    end
  end
 
  assign dac_shift = spi_sck & ~dac_ld;
 
  always @(posedge clk) begin
    if (reset) begin
      dac_sr <= 48'h0;
    end else begin
      if (dac_next) begin
        dac_sr[47:44] <= 4'b0011;
        dac_sr[43:40] <= 4'b0000;
        dac_sr[39:24] <= { ~dac_sample_l[15],
                            dac_sample_l[14:0] };
        dac_sr[23:20] <= 4'b0011;
        dac_sr[19:16] <= 4'b0001;
        dac_sr[15: 0] <= { ~dac_sample_r[15],
                            dac_sample_r[14:0] };
      end else begin
        if (dac_shift) begin
          dac_sr[47:1] <= dac_sr[46:0];
          dac_sr[0] <= 1'b0;
        end
      end
    end
  end
 
  assign dac_cs_n = dac_ld;
  assign dac_clr_n = ~reset;
 
  //------------------------------------------------------------
 
  //
  // amplifier controller
  //
 
  assign amp_cs_n = 1;
  assign amp_shdn = reset;
 
  //------------------------------------------------------------
 
  //
  // ADC controller
  //
 
  assign ad_conv = 0;
 
  //------------------------------------------------------------
 
  //
  // SPI data output
  //
 
  assign spi_mosi = dac_sr[47];
 
endmodule

Line No.	Rev	Author	Line
1	218	hellwig	`//`
2			`// spi.v -- SPI bus controller`
3			`//`
4
5
6			`module spi(clk, reset, spi_en,`
7			`dac_sample_l, dac_sample_r, dac_next,`
8			`spi_sck, spi_mosi,`
9			`dac_cs_n, dac_clr_n,`
10			`amp_cs_n, amp_shdn,`
11			`ad_conv);`
12			`// internal interface`
13			`input clk;`
14			`input reset;`
15			`input spi_en;`
16			`// DAC controller interface`
17			`input [15:0] dac_sample_l;`
18			`input [15:0] dac_sample_r;`
19			`output dac_next;`
20			`// external interface`
21			`output spi_sck;`
22			`output spi_mosi;`
23			`output dac_cs_n;`
24			`output dac_clr_n;`
25			`output amp_cs_n;`
26			`output amp_shdn;`
27			`output ad_conv;`
28
29			`//------------------------------------------------------------`
30
31			`//`
32			`// SPI timing and clock generator`
33			`//`
34
35			`reg [9:0] timing;`
36
37			`always @(posedge clk) begin`
38			`if (reset) begin`
39			`timing <= 10'h0;`
40			`end else begin`
41			`if (spi_en == 1'b0 && timing == 10'h0) begin`
42			`// put SPI on hold in state 0 if disabled`
43			`timing <= timing;`
44			`end else begin`
45			`// else step through the command cycle`
46			`timing <= timing + 1;`
47			`end`
48			`end`
49			`end`
50
51			`assign spi_sck = timing[0];`
52
53			`//------------------------------------------------------------`
54
55			`//`
56			`// DAC controller`
57			`//`
58
59			`reg dac_ld;`
60			`reg [47:0] dac_sr;`
61			`wire dac_shift;`
62
63			`assign dac_next = (timing[9:0] == 10'h001) ? 1 : 0;`
64
65			`always @(posedge clk) begin`
66			`if (reset) begin`
67			`dac_ld <= 1'b1;`
68			`end else begin`
69			`if (timing[9:0] == 10'h001) begin`
70			`dac_ld <= 1'b0;`
71			`end`
72			`if (timing[9:0] == 10'h031) begin`
73			`dac_ld <= 1'b1;`
74			`end`
75			`if (timing[9:0] == 10'h033) begin`
76			`dac_ld <= 1'b0;`
77			`end`
78			`if (timing[9:0] == 10'h063) begin`
79			`dac_ld <= 1'b1;`
80			`end`
81			`end`
82			`end`
83
84			`assign dac_shift = spi_sck & ~dac_ld;`
85
86			`always @(posedge clk) begin`
87			`if (reset) begin`
88			`dac_sr <= 48'h0;`
89			`end else begin`
90			`if (dac_next) begin`
91			`dac_sr[47:44] <= 4'b0011;`
92			`dac_sr[43:40] <= 4'b0000;`
93			`dac_sr[39:24] <= { ~dac_sample_l[15],`
94			`dac_sample_l[14:0] };`
95			`dac_sr[23:20] <= 4'b0011;`
96			`dac_sr[19:16] <= 4'b0001;`
97			`dac_sr[15: 0] <= { ~dac_sample_r[15],`
98			`dac_sample_r[14:0] };`
99			`end else begin`
100			`if (dac_shift) begin`
101			`dac_sr[47:1] <= dac_sr[46:0];`
102			`dac_sr[0] <= 1'b0;`
103			`end`
104			`end`
105			`end`
106			`end`
107
108			`assign dac_cs_n = dac_ld;`
109			`assign dac_clr_n = ~reset;`
110
111			`//------------------------------------------------------------`
112
113			`//`
114			`// amplifier controller`
115			`//`
116
117			`assign amp_cs_n = 1;`
118			`assign amp_shdn = reset;`
119
120			`//------------------------------------------------------------`
121
122			`//`
123			`// ADC controller`
124			`//`
125
126			`assign ad_conv = 0;`
127
128			`//------------------------------------------------------------`
129
130			`//`
131			`// SPI data output`
132			`//`
133
134			`assign spi_mosi = dac_sr[47];`
135
136			`endmodule`

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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [s3e-500/] [src/] [spi/] [spi.v] - Blame information for rev 230