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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [xsa-xst-3/] [doc/] [dac/] [README] - Blame information for rev 323

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Line No.	Rev	Author	Line
1	231	hellwig
2			`Timing Parameters`
3			`-----------------`
4
5			`clk = 50 MHz (20 nsec)`
6			`mclk = clk / 4 = 12.5 MHz (80 nsec)`
7			`sclk = mclk / 4 = 3.125 MHz (320 nsec)`
8			`lrck = sclk / 64 = 48.828 kHz (20.48 usec)`
9
10			`==>`
11
12			`fs = 48.828 kHz`
13			`mclk = 256 * fs = 12.5 MHz`
14			`sclk = 64 * fs = 3.125 MHz`
15

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