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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [cpu/] [cpu_bus.v] - Blame information for rev 314

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Line No. Rev Author Line
1 290 hellwig
//
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// cpu_bus.v -- the ECO32 CPU bus interface
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//
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`timescale 1ns/10ps
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`default_nettype none
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module cpu_bus(clk, rst,
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               bus_stb, bus_we, bus_addr,
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               bus_din, bus_dout, bus_ack, bus_irq,
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               cpu_stb, cpu_we, cpu_size, cpu_addr,
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               cpu_din, cpu_dout, cpu_ack, cpu_irq);
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    // bus interface
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    input clk;
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    input rst;
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    output reg bus_stb;
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    output reg bus_we;
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    output reg [31:2] bus_addr;
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    input [31:0] bus_din;
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    output reg [31:0] bus_dout;
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    input bus_ack;
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    input [15:0] bus_irq;
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    // CPU interface
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    input cpu_stb;
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    input cpu_we;
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    input [1:0] cpu_size;
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    input [31:0] cpu_addr;
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    output reg [31:0] cpu_din;
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    input [31:0] cpu_dout;
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    output reg cpu_ack;
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    output [15:0] cpu_irq;
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  reg state;
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  reg next_state;
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  reg [31:0] wbuf;
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  reg wbuf_we;
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  reg [31:0] wbuf_in;
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  // ctrl
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  always @(posedge clk) begin
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    if (rst) begin
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      state <= 0;
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    end else begin
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      state <= next_state;
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    end
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  end
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  // output
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  always @(*) begin
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    case (state)
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      1'b0:
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        if (~cpu_stb) begin
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          // no bus activity from cpu
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          bus_stb = 1'b0;
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          bus_we = 1'bx;
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          bus_addr[31:2] = 30'bx;
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          bus_dout[31:0] = 32'bx;
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          cpu_din[31:0] = 32'bx;
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          cpu_ack = 1'b0;
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          next_state = 1'b0;
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          wbuf_we = 1'b0;
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          wbuf_in[31:0] = 32'bx;
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        end else begin
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          // bus activated by cpu
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          if (~cpu_we) begin
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            // cpu read cycle
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            if (~cpu_size[1]) begin
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              if (~cpu_size[0]) begin
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                // cpu read byte
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                bus_stb = 1'b1;
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                bus_we = 1'b0;
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                bus_addr[31:2] = cpu_addr[31:2];
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                bus_dout[31:0] = 32'bx;
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                if (~cpu_addr[1]) begin
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                  if (~cpu_addr[0]) begin
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                    cpu_din[31:0] = { 24'h0, bus_din[31:24] };
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                  end else begin
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                    cpu_din[31:0] = { 24'h0, bus_din[23:16] };
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                  end
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                end else begin
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                  if (~cpu_addr[0]) begin
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                    cpu_din[31:0] = { 24'h0, bus_din[15: 8] };
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                  end else begin
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                    cpu_din[31:0] = { 24'h0, bus_din[ 7: 0] };
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                  end
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                end
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                cpu_ack = bus_ack;
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                next_state = 1'b0;
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                wbuf_we = 1'b0;
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                wbuf_in[31:0] = 32'bx;
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              end else begin
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                // cpu read halfword
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                bus_stb = 1'b1;
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                bus_we = 1'b0;
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                bus_addr[31:2] = cpu_addr[31:2];
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                bus_dout[31:0] = 32'bx;
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                if (~cpu_addr[1]) begin
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                  cpu_din[31:0] = { 16'h0, bus_din[31:16] };
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                end else begin
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                  cpu_din[31:0] = { 16'h0, bus_din[15: 0] };
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                end
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                cpu_ack = bus_ack;
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                next_state = 1'b0;
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                wbuf_we = 1'b0;
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                wbuf_in[31:0] = 32'bx;
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              end
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            end else begin
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              // cpu read word
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              bus_stb = 1'b1;
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              bus_we = 1'b0;
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              bus_addr[31:2] = cpu_addr[31:2];
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              bus_dout[31:0] = 32'bx;
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              cpu_din[31:0] = bus_din[31:0];
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              cpu_ack = bus_ack;
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              next_state = 1'b0;
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              wbuf_we = 1'b0;
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              wbuf_in[31:0] = 32'bx;
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            end
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          end else begin
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            // cpu write cycle
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            if (~cpu_size[1]) begin
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              if (~cpu_size[0]) begin
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                // cpu write byte
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                // part 1: read word into word buffer
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                bus_stb = 1'b1;
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                bus_we = 1'b0;
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                bus_addr[31:2] = cpu_addr[31:2];
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                bus_dout[31:0] = 32'bx;
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                cpu_din[31:0] = 32'bx;
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                cpu_ack = 1'b0;
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                if (~bus_ack) begin
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                  next_state = 1'b0;
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                end else begin
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                  next_state = 1'b1;
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                end
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                wbuf_we = 1'b1;
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                if (~cpu_addr[1]) begin
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                  if (~cpu_addr[0]) begin
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                    wbuf_in[31:0] = { cpu_dout[7:0], bus_din[23:16],
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                                      bus_din[15:8], bus_din[7:0] };
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                  end else begin
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                    wbuf_in[31:0] = { bus_din[31:24], cpu_dout[7:0],
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                                      bus_din[15:8], bus_din[7:0] };
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                  end
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                end else begin
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                  if (~cpu_addr[0]) begin
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                    wbuf_in[31:0] = { bus_din[31:24], bus_din[23:16],
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                                      cpu_dout[7:0], bus_din[7:0] };
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                  end else begin
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                    wbuf_in[31:0] = { bus_din[31:24], bus_din[23:16],
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                                      bus_din[15:8], cpu_dout[7:0] };
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                  end
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                end
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              end else begin
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                // cpu write halfword
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                // part 1: read word into word buffer
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                bus_stb = 1'b1;
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                bus_we = 1'b0;
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                bus_addr[31:2] = cpu_addr[31:2];
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                bus_dout[31:0] = 32'bx;
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                cpu_din[31:0] = 32'bx;
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                cpu_ack = 1'b0;
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                if (~bus_ack) begin
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                  next_state = 1'b0;
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                end else begin
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                  next_state = 1'b1;
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                end
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                wbuf_we = 1'b1;
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                if (~cpu_addr[1]) begin
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                  wbuf_in[31:0] = { cpu_dout[15:0], bus_din[15:0] };
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                end else begin
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                  wbuf_in[31:0] = { bus_din[31:16], cpu_dout[15:0] };
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                end
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              end
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            end else begin
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              // cpu write word
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              bus_stb = 1'b1;
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              bus_we = 1'b1;
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              bus_addr[31:2] = cpu_addr[31:2];
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              bus_dout[31:0] = cpu_dout[31:0];
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              cpu_din[31:0] = 32'bx;
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              cpu_ack = bus_ack;
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              next_state = 1'b0;
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              wbuf_we = 1'b0;
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              wbuf_in[31:0] = 32'bx;
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            end
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          end
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        end
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      1'b1:
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        begin
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          // cpu write halfword or byte
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          // part 2: write word from word buffer
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          bus_stb = 1'b1;
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          bus_we = 1'b1;
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          bus_addr[31:2] = cpu_addr[31:2];
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          bus_dout[31:0] = wbuf[31:0];
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          cpu_din[31:0] = 32'bx;
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          cpu_ack = bus_ack;
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          if (~bus_ack) begin
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            next_state = 1'b1;
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          end else begin
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            next_state = 1'b0;
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          end
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          wbuf_we = 1'b0;
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          wbuf_in[31:0] = 32'bx;
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        end
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    endcase
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  end
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  // word buffer
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  always @(posedge clk) begin
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    if (wbuf_we) begin
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      wbuf[31:0] <= wbuf_in[31:0];
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    end
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  end
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  // interrupt requests
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  assign cpu_irq[15:0] = bus_irq[15:0];
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endmodule

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