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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsk/] [dsk.v] - Blame information for rev 314

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//
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// dsk.v -- parallel ATA (IDE) disk interface
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//
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`timescale 1ns/10ps
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`default_nettype none
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module dsk(clk, rst,
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           stb, we, addr,
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           data_in, data_out,
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           ack, irq,
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           ata_d, ata_a, ata_cs0_n, ata_cs1_n,
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           ata_dior_n, ata_diow_n, ata_intrq,
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           ata_dmarq, ata_dmack_n, ata_iordy);
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    // internal interface signals
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    input clk;
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    input rst;
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    input stb;
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    input we;
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    input [19:2] addr;
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    input [31:0] data_in;
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    output [31:0] data_out;
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    output ack;
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    output irq;
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    // external interface signals
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    inout [15:0] ata_d;
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    output [2:0] ata_a;
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    output ata_cs0_n, ata_cs1_n;
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    output ata_dior_n, ata_diow_n;
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    input ata_intrq;
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    input ata_dmarq;
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    output ata_dmack_n;
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    input ata_iordy;
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  wire bus_wait;
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  ata_ctrl ata_ctrl_1(
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    .clk(clk),
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    .reset(rst),
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    .bus_en(stb),
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    .bus_wr(we),
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    .bus_addr(addr),
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    .bus_din(data_in),
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    .bus_dout(data_out),
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    .bus_wait(bus_wait),
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    .bus_irq(irq),
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    .ata_d(ata_d),
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    .ata_a(ata_a),
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    .ata_cs0_n(ata_cs0_n),
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    .ata_cs1_n(ata_cs1_n),
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    .ata_dior_n(ata_dior_n),
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    .ata_diow_n(ata_diow_n),
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    .ata_intrq(ata_intrq),
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    .ata_dmarq(ata_dmarq),
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    .ata_dmack_n(ata_dmack_n),
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    .ata_iordy(ata_iordy)
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  );
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  assign ack = stb & ~bus_wait;
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endmodule

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