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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsp/] [common/] [timing.v] - Blame information for rev 323

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//
// timing.v -- timing generator
//
 
 
`timescale 1ns/10ps
`default_nettype none
 
 
module timing(clk, pixclk,
              txtrow, txtcol,
              chrrow, chrcol,
              blank, hsync, vsync, blink);
    input clk;
    output pixclk;
    output [4:0] txtrow;
    output [6:0] txtcol;
    output [3:0] chrrow;
    output [2:0] chrcol;
    output blank;
    output hsync;
    output vsync;
    output reg blink;
 
  reg pclk;
  reg [9:0] hcnt;
  reg hblank, hsynch;
  reg [9:0] vcnt;
  reg vblank, vsynch;
  reg [5:0] bcnt;
 
  always @(posedge clk) begin
    pclk <= ~pclk;
  end
 
  assign pixclk = pclk;
 
  always @(posedge clk) begin
    if (pclk == 1) begin
      if (hcnt == 10'd799) begin
        hcnt <= 10'd0;
        hblank <= 1;
      end else begin
        hcnt <= hcnt + 1;
      end
      if (hcnt == 10'd639) begin
        hblank <= 0;
      end
      if (hcnt == 10'd655) begin
        hsynch <= 0;
      end
      if (hcnt == 10'd751) begin
        hsynch <= 1;
      end
    end
  end
 
  always @(posedge clk) begin
    if (pclk == 1 && hcnt == 10'd799) begin
      if (vcnt == 10'd524) begin
        vcnt <= 10'd0;
        vblank <= 1;
      end else begin
        vcnt <= vcnt + 1;
      end
      if (vcnt == 10'd479) begin
        vblank <= 0;
      end
      if (vcnt == 10'd489) begin
        vsynch <= 0;
      end
      if (vcnt == 10'd491) begin
        vsynch <= 1;
      end
    end
  end
 
  always @(posedge clk) begin
    if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin
      if (bcnt == 6'd59) begin
        bcnt <= 6'd0;
        blink <= 1;
      end else begin
        bcnt <= bcnt + 1;
      end
      if (bcnt == 6'd29) begin
        blink <= 0;
      end
    end
  end
 
  assign blank = hblank & vblank;
 
  assign hsync = hsynch;
  assign vsync = vsynch;
 
  assign txtrow[4:0] = vcnt[8:4];
  assign txtcol[6:0] = hcnt[9:3];
  assign chrrow[3:0] = vcnt[3:0];
  assign chrcol[2:0] = hcnt[2:0];
 
endmodule

Line No.	Rev	Author	Line
1	123	hellwig	`//`
2			`// timing.v -- timing generator`
3			`//`
4
5
6	290	hellwig	`timescale 1ns/10ps
7			`default_nettype none
8
9
10	27	hellwig	`module timing(clk, pixclk,`
11			`txtrow, txtcol,`
12			`chrrow, chrcol,`
13			`blank, hsync, vsync, blink);`
14			`input clk;`
15			`output pixclk;`
16			`output [4:0] txtrow;`
17			`output [6:0] txtcol;`
18			`output [3:0] chrrow;`
19			`output [2:0] chrcol;`
20			`output blank;`
21			`output hsync;`
22			`output vsync;`
23			`output reg blink;`
24
25			`reg pclk;`
26			`reg [9:0] hcnt;`
27			`reg hblank, hsynch;`
28			`reg [9:0] vcnt;`
29			`reg vblank, vsynch;`
30			`reg [5:0] bcnt;`
31
32			`always @(posedge clk) begin`
33			`pclk <= ~pclk;`
34			`end`
35
36			`assign pixclk = pclk;`
37
38			`always @(posedge clk) begin`
39			`if (pclk == 1) begin`
40			`if (hcnt == 10'd799) begin`
41			`hcnt <= 10'd0;`
42			`hblank <= 1;`
43			`end else begin`
44			`hcnt <= hcnt + 1;`
45			`end`
46			`if (hcnt == 10'd639) begin`
47			`hblank <= 0;`
48			`end`
49			`if (hcnt == 10'd655) begin`
50			`hsynch <= 0;`
51			`end`
52			`if (hcnt == 10'd751) begin`
53			`hsynch <= 1;`
54			`end`
55			`end`
56			`end`
57
58			`always @(posedge clk) begin`
59			`if (pclk == 1 && hcnt == 10'd799) begin`
60			`if (vcnt == 10'd524) begin`
61			`vcnt <= 10'd0;`
62			`vblank <= 1;`
63			`end else begin`
64			`vcnt <= vcnt + 1;`
65			`end`
66			`if (vcnt == 10'd479) begin`
67			`vblank <= 0;`
68			`end`
69			`if (vcnt == 10'd489) begin`
70			`vsynch <= 0;`
71			`end`
72			`if (vcnt == 10'd491) begin`
73			`vsynch <= 1;`
74			`end`
75			`end`
76			`end`
77
78			`always @(posedge clk) begin`
79			`if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin`
80			`if (bcnt == 6'd59) begin`
81			`bcnt <= 6'd0;`
82			`blink <= 1;`
83			`end else begin`
84			`bcnt <= bcnt + 1;`
85			`end`
86			`if (bcnt == 6'd29) begin`
87			`blink <= 0;`
88			`end`
89			`end`
90			`end`
91
92			`assign blank = hblank & vblank;`
93
94			`assign hsync = hsynch;`
95			`assign vsync = vsynch;`
96
97			`assign txtrow[4:0] = vcnt[8:4];`
98			`assign txtcol[6:0] = hcnt[9:3];`
99			`assign chrrow[3:0] = vcnt[3:0];`
100			`assign chrcol[2:0] = hcnt[2:0];`
101
102			`endmodule`

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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsp/] [common/] [timing.v] - Blame information for rev 323