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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [kbd/] [kbd.v] - Blame information for rev 288

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Line No. Rev Author Line
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//
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// kbd.v -- PC keyboard interface
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//
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module kbd(clk, reset,
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           en, wr, addr,
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           data_in, data_out,
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           wt, irq,
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           ps2_clk, ps2_data);
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    // internal interface
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    input clk;
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    input reset;
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    input en;
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    input wr;
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    input addr;
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    input [7:0] data_in;
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    output [7:0] data_out;
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    output wt;
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    output irq;
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    // external interface
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    input ps2_clk;
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    input ps2_data;
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  wire [7:0] keyboard_data;
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  wire keyboard_rdy;
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  reg [7:0] data;
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  reg rdy;
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  reg ien;
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  reg [7:2] other_bits;
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  keyboard keyboard1(
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    .ps2_clk(ps2_clk),
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    .ps2_data(ps2_data),
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    .clk(clk),
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    .reset(reset),
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    .keyboard_data(keyboard_data[7:0]),
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    .keyboard_rdy(keyboard_rdy)
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  );
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  always @(posedge clk) begin
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    if (reset == 1) begin
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      data <= 8'h00;
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      rdy <= 0;
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      ien <= 0;
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      other_bits <= 6'b000000;
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    end else begin
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      if (keyboard_rdy == 1) begin
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        data <= keyboard_data;
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      end
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      if (keyboard_rdy == 1 ||
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          (en == 1 && wr == 0 && addr == 1)) begin
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        rdy <= keyboard_rdy;
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      end
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      if (en == 1 && wr == 1 && addr == 0) begin
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        rdy <= data_in[0];
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        ien <= data_in[1];
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        other_bits <= data_in[7:2];
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      end
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    end
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  end
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  assign data_out =
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    (addr == 0) ? { other_bits[7:2], ien, rdy } : data[7:0];
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  assign wt = 1'b0;
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  assign irq = ien & rdy;
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endmodule

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