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////////////////////////////////////////////////////////////////////////////
//
// Create Date:    02/11/07
// Last Change:    01/22/12
// Design Name:    DDR SDRAM memory controller
// Module Name:    ddr_sdram
// Description:    memory controller for DDR SDRAM
//                 hard coded for 8 Meg x 16 x 4 banks
//
// Revision:
// Revision 0.01 - File Created
//
// Development platform: Spartan-3E Starter kit
//
// Copyright (C) 2007, Rick Huang
//
// Modifications by Hellwig Geisse, 2012
//   - sd_CK_P and sd_CK_N supplied by this module
//   - DDR output registers for sd_CK_P and sd_CK_N added
//   - sd_CLK_O deleted
//   - debug output deleted
//   - burst mode sections of the state machine deleted
//     (have been commented out already)
//   - additional states SD_RD_DONE_1 and SD_WR_DONE_1 inserted
//     (in order to stretch the wACK_O signal, which is to be
//     recognized by external circuits clocked with 50 MHz)
//   - four "write byte" signals added to interface
//     (to allow 8 and 16 bit write operations too)
//   - mask registers UDM_reg_O and LDM_reg_O deleted
//   - DDR output registers for sd_UDM_O and sd_LDM_O added
//   - data_sample_en and its associated multiplexer removed
//     (apparently a debugging vehicle)
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
// MA  02110-1301  USA
//
////////////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/10ps
`default_nettype none
 
 
module ddr_sdram(sd_CK_P, sd_CK_N,
                 sd_A_O, sd_BA_O, sd_D_IO,
                 sd_RAS_O, sd_CAS_O, sd_WE_O,
                 sd_UDM_O, sd_LDM_O,
                 sd_UDQS_IO, sd_LDQS_IO,
                 sd_CS_O, sd_CKE_O,
                 clk0, clk90,
                 clk180, clk270,
                 reset,
                 wADR_I, wSTB_I, wWE_I, wWRB_I,
                 wDAT_I, wDAT_O, wACK_O);
        // interface to DDR SDRAM memory
        output  sd_CK_P;
        output  sd_CK_N;
        output  [12:0] sd_A_O;
        output  [1:0]  sd_BA_O;
        inout   [15:0] sd_D_IO;
        output  sd_RAS_O;
        output  sd_CAS_O;
        output  sd_WE_O;
        output  sd_UDM_O;
        output  sd_LDM_O;
        inout   sd_UDQS_IO;
        inout   sd_LDQS_IO;
        output  sd_CS_O;
        output  sd_CKE_O;
        // internal interface signals
        input   clk0;
        input   clk90;
        input   clk180;
        input   clk270;
        input   reset;
        // A[25:24] = bank[1:0]
        // A[23:11] = row[12:0]
        // A[10: 2] = col[9:1]
        // (a specific combination of the 2+13+9=24 bits adresses
        // a 32-bit word which is transmitted as a burst of two
        // consecutive 16-bit halfwords in one clock cycle)
        input   [25:2] wADR_I;
        input   wSTB_I;
        input   wWE_I;
        input   [3:0] wWRB_I;
        input   [31:0] wDAT_I;
        output  [31:0] wDAT_O;
        output  wACK_O;
 
        // Local data storage
        reg             [5:0] sd_state;
        reg             [3:0] init_state;
        reg             [5:0] wait_count;
        reg             [14:0] init_wait_count;
        reg             [12:0] sd_A_O;
        reg             [1:0] sd_BA_O;
        reg             [12:0] mode_reg;
        reg             sd_RAS_O;
        reg             sd_CAS_O;
        reg             sd_WE_O;
        reg             sd_CS_O;
        reg             sd_CKE_O;
        reg             wACK_O;
 
        reg             [9:0] refresh_counter;
        reg             [3:0] refresh_queue;     // Number of refresh command to queue
        reg             refresh_now;
        reg             refresh_ack;
 
        reg             [31:0] D_rd_reg;
        reg             DQS_state;
        reg             DQS_oe;                 // 1 for output
        reg             D_oe;                   // 1 for output enable
 
        reg             [31:0] D_wr_reg; // Data write buffer
        reg             [3:0] D_mask_reg;        // data mask buffer
 
 
/***************************************************
 * SD ram clock source
 ***************************************************/
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_CK_P (
                .Q(sd_CK_P),
                .C0(clk180),
                .C1(clk0),
                .CE(1'b1),
                .D0(1'b1),
                .D1(1'b0),
                .R(1'b0),
                .S(1'b0)
        );
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_CK_N (
                .Q(sd_CK_N),
                .C0(clk0),
                .C1(clk180),
                .CE(1'b1),
                .D0(1'b1),
                .D1(1'b0),
                .R(1'b0),
                .S(1'b0)
        );
 
/***************************************************
 * De-duplex of the data path
 * For some reason, for read, the output is CL=2.5, not CL=2
 * Thus, catching of the data is 1/2 a cycle late.
 * Flip the clk0 and clk180, 1/2 cycle delay catched
 * on data_mux_latch
 ***************************************************/
 
        // Data from SDRAM will be loaded at {data_mux_out[31:0]}
        wire    [31:0] data_mux_out;
        wire    [15:0] iddr_conn;
        wire    [15:0] oddr_conn;
 
 
        generate
        genvar i;
 
                for(i=0;i<16;i=i+1)
                begin : iou
                        IDDR2 #(
                                .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
                                .INIT_Q0(1'b0),                 // Sets initial state of the Q0 output to 1'b0 or 1'b1
                                .INIT_Q1(1'b0),                 // Sets initial state of the Q1 output to 1'b0 or 1'b1
                                .SRTYPE("SYNC")                 // Specifies "SYNC" or "ASYNC" set/reset
                        ) IDDR2_inst (
                                .Q0(data_mux_out[i]),                           // C0 clock
                                .Q1(data_mux_out[i+16]),                        // C1 clock
                                .C0(clk180),
                                .C1(clk0),
                                .CE(1'b1),                              // Always enabled
                                .D(iddr_conn[i]),               // 1-bit DDR data input
                                .R(1'b0),                               // 1-bit reset input
                                .S(1'b0)                                // 1-bit set input
                        );
 
                        ODDR2 #(
                                .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
                                .INIT(1'b0),                    // Sets initial state of the Q output to 1'b0 or 1'b1
                                .SRTYPE("SYNC")                 // Specifies "SYNC" or "ASYNC" set/reset
                        ) ODDR2_inst (
                                .Q(oddr_conn[i]),               // 1-bit DDR output data
                                .C0(clk90),                     // 1-bit clock input
                                .C1(clk270),            // 1-bit clock input
                                .CE(1'b1),                              // 1-bit clock enable input
                                .D0(D_wr_reg[i]),               // (associated with C0)
                                .D1(D_wr_reg[i+16]),    // (associated with C1)
                                .R(1'b0),                               // 1-bit reset input
                                .S(1'b0)                                // 1-bit set input
                        );
 
                        IOBUF #(
                                .DRIVE(4),                              // Specify the output drive strength
                                .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay
                                .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"
                                .IOSTANDARD("DEFAULT"), // Specify the I/O standard
                                .SLEW("SLOW")                   // Specify the output slew rate
                        ) IOBUF_inst (
                                .O(iddr_conn[i]),               // Buffer output
                                .IO(sd_D_IO[i]),                // Buffer inout port (connect directly to top-level port)
                                .I(oddr_conn[i]),               // Buffer input
                                .T(~D_oe)                               // 3-state enable input
                        );
                end
        endgenerate
 
 
        wire sd_UDQS_O;
        wire sd_LDQS_O;
 
                ODDR2 #(
                        .DDR_ALIGNMENT("NONE"),
                        .INIT(1'b0),
                        .SRTYPE("SYNC")
                ) ODDR2_inst_UDQS (
                        .Q(sd_UDQS_O),
                        .C0(clk180),
                        .C1(clk0),
                        .CE(1'b1),
                        .D0(DQS_state),
                        .D1(1'b0),
                        .R(1'b0),
                        .S(1'b0)
                );
 
                ODDR2 #(
                        .DDR_ALIGNMENT("NONE"),
                        .INIT(1'b0),
                        .SRTYPE("SYNC")
                ) ODDR2_inst_LDQS (
                        .Q(sd_LDQS_O),
                        .C0(clk180),
                        .C1(clk0),
                        .CE(1'b1),
                        .D0(DQS_state),
                        .D1(1'b0),
                        .R(1'b0),
                        .S(1'b0)
                );
 
                IOBUF #(
                        .DRIVE(4),
                        .IBUF_DELAY_VALUE("0"),
                        .IFD_DELAY_VALUE("AUTO"),
                        .IOSTANDARD("DEFAULT"),
                        .SLEW("SLOW")
                ) IOBUF_inst_UDQS (
                        // .O() intentionally not connected
                        .IO(sd_UDQS_IO),
                        .I(sd_UDQS_O),
                        .T(~DQS_oe)
                );
 
                IOBUF #(
                        .DRIVE(4),
                        .IBUF_DELAY_VALUE("0"),
                        .IFD_DELAY_VALUE("AUTO"),
                        .IOSTANDARD("DEFAULT"),
                        .SLEW("SLOW")
                ) IOBUF_inst_LDQS (
                        // .O() intentionally not connected
                        .IO(sd_LDQS_IO),
                        .I(sd_LDQS_O),
                        .T(~DQS_oe)
                );
 
 
        reg [31:0] data_mux_latch;
        always @ (posedge clk180)
        begin
                data_mux_latch <= data_mux_out;
        end
 
/***************************************************
 * Data bus flow direction control
 ***************************************************/
 
        assign wDAT_O = D_rd_reg[31:0];
 
        // Mask output
 
        wire            UDM_conn;
        wire            LDM_conn;
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_UDM (
                .Q(UDM_conn),
                .C0(clk90),
                .C1(clk270),
                .CE(1'b1),
                .D0(~D_mask_reg[1]),
                .D1(~D_mask_reg[3]),
                .R(1'b0),
                .S(1'b0)
        );
 
        ODDR2 #(
                .DDR_ALIGNMENT("NONE"),
                .INIT(1'b0),
                .SRTYPE("SYNC")
        ) ODDR2_inst_LDM (
                .Q(LDM_conn),
                .C0(clk90),
                .C1(clk270),
                .CE(1'b1),
                .D0(~D_mask_reg[0]),
                .D1(~D_mask_reg[2]),
                .R(1'b0),
                .S(1'b0)
        );
 
        IOBUF #(
                .DRIVE(4),
                .IBUF_DELAY_VALUE("0"),
                .IFD_DELAY_VALUE("AUTO"),
                .IOSTANDARD("DEFAULT"),
                .SLEW("SLOW")
        ) IOBUF_inst_UDM (
                // .O() intentionally not connected
                .IO(sd_UDM_O),
                .I(UDM_conn),
                .T(1'b0)
        );
 
        IOBUF #(
                .DRIVE(4),
                .IBUF_DELAY_VALUE("0"),
                .IFD_DELAY_VALUE("AUTO"),
                .IOSTANDARD("DEFAULT"),
                .SLEW("SLOW")
        ) IOBUF_inst_LDM (
                // .O() intentionally not connected
                .IO(sd_LDM_O),
                .I(LDM_conn),
                .T(1'b0)
        );
 
 
/***************************************************
 * Main tx/rx state machine
 ***************************************************/
 
        /* Timing */
        parameter WAIT_TIME = 5'd5;
        parameter INIT_WAIT = 15'h3000;
        parameter INIT_CLK_EN_WAIT = 15'h10;
        parameter WAIT_CMD_MAX = 6'b100000;
        parameter REFRESH_WAIT = WAIT_CMD_MAX - 6'd7;
        parameter ACCESS_WAIT = WAIT_CMD_MAX - 6'd1;
        parameter CAS_WAIT = WAIT_CMD_MAX - 6'd3;
        parameter AVG_REFRESH_DUR = 10'd700;
 
        /* Main state machine */
        parameter       SD_IDLE = 0,
                                SD_INIT = 1,
                                SD_INIT_WAIT = 2,
                                SD_PRECHG_ALL = 3,
                                SD_PRECHG_ALL1 = 4,
                                SD_AUTO_REF = 5,
                                SD_AUTO_REF1 = 6,
                                SD_AUTO_REF_ACK = 7,
                                SD_LD_MODE = 8,
                                SD_LD_MODE1 = 9,
                                SD_RD_START = 10,
                                SD_RD_COL = 11,
                                SD_RD_CAS_WAIT = 12,
                                SD_RD_LATCH = 13,
                                SD_RD_LATCH1 = 14,
                                SD_RD_DONE = 15,
                                SD_WR_START = 16,
                                SD_WR_COL = 17,
                                SD_WR_CAS_WAIT = 18,
                                SD_WR_LATCH = 19,
                                SD_WR_LATCH1 = 20,
                                SD_WR_DONE = 21,
                                SD_RD_DONE_1 = 22,
                                SD_WR_DONE_1 = 23;
 
        /* Initialization state machine */
        parameter       SI_START = 0,
                                SI_PRECHG = 1,
                                SI_LOAD_EX_MODE = 2,
                                SI_LOAD_MODE = 3,
                                SI_LOAD_MODE2 = 4,
                                SI_PRECHG2 = 5,
                                SI_AUTO_REF = 6,
                                SI_AUTO_REF2 = 7,
                                SI_DONE = 8;
 
 
always @ (posedge clk0)
begin
        if(reset)
        begin
                sd_state <= SD_INIT;
                init_state <= SI_START;
        end else
        begin
                wait_count <= wait_count + 1;
 
                case (sd_state)
                        SD_INIT:                                                // Initialize, wait until INIT_WAIT
                        begin
                                case (init_state)
                                        SI_START:
                                        begin
                                                sd_state <= SD_INIT_WAIT;
                                                init_state <= SI_PRECHG;
                                                sd_RAS_O <= 1;
                                                sd_CAS_O <= 1;
                                                sd_WE_O <= 1;
                                                sd_CS_O <= 1;
                                                sd_CKE_O <= 0;
                                                init_wait_count <= 16'd0;
                                        end
                                        SI_PRECHG:
                                        begin
                                                sd_state <= SD_PRECHG_ALL;
                                                init_state <= SI_LOAD_EX_MODE;
                                        end
                                        SI_LOAD_EX_MODE:
                                        begin
                                                // Normal operation
                                                mode_reg <= 13'b0000000000000;
                                                sd_BA_O <= 2'b01;
                                                sd_state <= SD_LD_MODE;
                                                init_state <= SI_LOAD_MODE;
                                        end
                                        SI_LOAD_MODE:
                                        begin
                                                // CAS = 2, Reset DLL, Burst = 2, sequential
                                                mode_reg <= {6'b000010, 3'b010, 1'b0, 3'b001};
                                                sd_BA_O <= 2'b00;
                                                sd_state <= SD_LD_MODE;
                                                init_state <= SI_LOAD_MODE2;
                                        end
                                        SI_LOAD_MODE2:
                                        begin
                                                // CAS = 2, NO Reset DLL, Burst = 2, sequential
                                                mode_reg <= {6'b000000, 3'b010, 1'b0, 3'b001};
                                                sd_BA_O <= 2'b00;
                                                sd_state <= SD_LD_MODE;
                                                init_state <= SI_PRECHG2;
                                        end
                                        SI_PRECHG2:
                                        begin
                                                sd_state <= SD_PRECHG_ALL;
                                                init_state <= SI_AUTO_REF;
                                        end
                                        SI_AUTO_REF:
                                        begin
                                                sd_state <= SD_AUTO_REF;
                                                init_state <= SI_AUTO_REF2;
                                        end
                                        SI_AUTO_REF2:
                                        begin
                                                sd_state <= SD_AUTO_REF;
                                                init_state <= SI_DONE;
                                        end
                                        SI_DONE:
                                        begin
                                                init_state <= SI_DONE;
                                                sd_state <= SD_IDLE;
                                        end
                                        default:
                                                init_state <= SI_START;
                                endcase
                        end
                        // ** Waiting for SDRAM waking up *****************************
                        SD_INIT_WAIT:
                        begin
                                init_wait_count <= init_wait_count + 1;
                                if(init_wait_count == INIT_WAIT)
                                begin
                                        sd_state <= SD_INIT;
                                end
                                if(init_wait_count == INIT_CLK_EN_WAIT)
                                begin
                                        sd_CKE_O <= 1;                          // Wake up the SDRAM
                                end
                        end
                        // ** Precharge command ***************************************
                        SD_PRECHG_ALL:
                        begin
                                sd_state <= SD_PRECHG_ALL1;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 0;
                                sd_CS_O <= 0;
                                sd_A_O[10] <= 1;                                // Command for precharge all
                        end
                        SD_PRECHG_ALL1:
                        begin
                                sd_CS_O <= 1;
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_state <= SD_IDLE;                    // Precharge takes 15nS before next command
                        end
                        // ** Load mode register **************************************
                        SD_LD_MODE:
                        begin
                                sd_state <= SD_LD_MODE1;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 0;
                                sd_WE_O <= 0;
                                sd_CS_O <= 0;
                                sd_A_O[12:0] <= mode_reg;
                        end
                        SD_LD_MODE1:
                        begin
                                sd_CS_O <= 1;
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;                                   // Load Mode takes 12nS
                                sd_state <= SD_IDLE;                    // Add wait if needed
                        end
                        // ** Auto refresh command ************************************
                        SD_AUTO_REF:
                        begin
                                sd_state <= SD_AUTO_REF1;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 0;
                                sd_WE_O <= 1;
                                sd_CS_O <= 0;
                                wait_count <= REFRESH_WAIT;
                        end
                        SD_AUTO_REF1:
                        begin
                                sd_CS_O <= 1;                                   // Issue NOP during wait
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                if(wait_count[5] == 1)                  // Time up, return to idle
                                begin
                                        sd_state <= SD_AUTO_REF_ACK;
                                        refresh_ack <= 1;
                                end
                        end
                        SD_AUTO_REF_ACK:                                        // Interlocking state
                        begin
                                sd_state <= SD_IDLE;
                                refresh_ack <= 0;
                        end
                        // ** Read cycle **********************************************
                        SD_RD_START:
                        begin
                                sd_state <= SD_RD_COL;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_CS_O <= 0;
                                sd_BA_O[1:0] <= wADR_I[25:24];
                                sd_A_O[12:0] <= wADR_I[23:11];
                                wait_count <= ACCESS_WAIT;
                                D_oe <= 0;                                               // Not driving the bus
                                DQS_state <= 0;
                        end
                        SD_RD_COL:
                        begin
                                if(wait_count[5] != 1)
                                begin
                                        sd_CS_O <= 1;                   // NOP command during access wait               
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 1;
                                        sd_WE_O <= 1;
                                end else
                                begin
                                        sd_CS_O <= 0;                            // Access column 
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 0;
                                        sd_WE_O <= 1;
                                        sd_state <= SD_RD_CAS_WAIT;
                                        sd_A_O[9:1] <= wADR_I[10:2];
                                        sd_A_O[10] <= 1;                        // Use auto-precharge
                                        sd_A_O[0] <= 0;
                                        wait_count <= CAS_WAIT;
                                        DQS_oe <= 0;                     // Set DQS for input
                                end
                        end
                        SD_RD_CAS_WAIT:
                        begin                                                           // Wait until DQS signal there is data
                                if(wait_count[5] != 1)
                                begin
                                        sd_CS_O <= 1;                           // NOP command during access wait               
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 1;
                                        sd_WE_O <= 1;
                                end else
                                begin
                                        sd_state <= SD_RD_LATCH;
                                end
                        end
                        SD_RD_LATCH:
                        begin
                                D_rd_reg <= data_mux_latch[31:0];
                                wACK_O <= 1;
                                sd_state <= SD_RD_DONE;
                        end
                        SD_RD_DONE:
                        begin
                                wACK_O <= 1;
                                sd_state <= SD_RD_DONE_1;
                                DQS_state <= 0;
                                DQS_oe <= 1;    // Set DQS back to output
                        end
                        SD_RD_DONE_1:
                        begin
                                wACK_O <= 0;
                                sd_state <= SD_IDLE;
                        end
                        // ** Write cycle *********************************************
                        SD_WR_START:
                        begin                                                   // Open the bank - ACTIVE command
                                sd_state <= SD_WR_COL;
                                sd_RAS_O <= 0;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_CS_O <= 0;
                                sd_BA_O[1:0] <= wADR_I[25:24];
                                sd_A_O[12:0] <= wADR_I[23:11];
                                D_wr_reg <= wDAT_I;
                                D_mask_reg <= wWRB_I;
                                wait_count <= ACCESS_WAIT;
                                DQS_state <= 0;
                        end
                        SD_WR_COL:
                        begin
                                if(wait_count[5] != 1)
                                begin
                                        sd_CS_O <= 1;                   // NOP command during access wait               
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 1;
                                        sd_WE_O <= 1;
                                end else
                                begin
                                        sd_CS_O <= 0;                    // Access column 
                                        sd_RAS_O <= 1;
                                        sd_CAS_O <= 0;
                                        sd_WE_O <= 0;
                                        DQS_oe <= 1;
                                        sd_state <= SD_WR_CAS_WAIT;
                                        sd_A_O[9:1] <= wADR_I[10:2];
                                        sd_A_O[10] <= 1;                // Use auto-precharge
                                        sd_A_O[0] <= 0;
                                end
                        end
                        SD_WR_CAS_WAIT:
                        begin                                                   // Wait until DQS signal there is data
                                sd_state <= SD_WR_LATCH;
                                DQS_state <= 1;                 // Start with DQS low
                                D_oe <= 1;                              // Drive the data bus
                                sd_CS_O <= 1;
                                sd_RAS_O <= 1;
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                        end
                        SD_WR_LATCH:
                        begin
                                sd_state <= SD_WR_LATCH1;
                                DQS_state <= 0;
                        end
                        SD_WR_LATCH1:
                        begin
                                sd_state <= SD_WR_DONE;
                                DQS_state <= 0;
                                wACK_O <= 1;
                        end
                        SD_WR_DONE:
                        begin
                                D_oe <= 0;
                                wACK_O <= 1;
                                sd_state <= SD_WR_DONE_1;
                        end
                        SD_WR_DONE_1:
                        begin
                                wACK_O <= 0;
                                sd_state <= SD_IDLE;
                        end
                    // Wishbone transfer is done during idle time
                        SD_IDLE:                                                /* Idle/sleep process */
                        begin
                                sd_RAS_O <= 1;                          // Set for NOP by default
                                sd_CAS_O <= 1;
                                sd_WE_O <= 1;
                                sd_CS_O <= 1;
                                if(init_state != SI_DONE)       // If still in init cycle, go back and work
                                        sd_state <= SD_INIT;
                                else if(wSTB_I && !wWE_I)                               // Start of a read command
                                        sd_state <= SD_RD_START;
                                else if(wSTB_I && wWE_I)        // Start of a write command
                                        sd_state <= SD_WR_START;
                                else if(refresh_now)                                    // Refresh is the last command
                                        sd_state <= SD_AUTO_REF;
                        end
 
                        default:
                                sd_state <= SD_IDLE;
                endcase
        end
end
 
/* Seperate always block for refresh timer */
/* The idea is to queue as many as 8 refresh command as possible if the bus is
 * free */
always @ (posedge clk0)
begin
        if(refresh_ack)
        begin
                refresh_now <= 0;
                refresh_queue <= refresh_queue + 4'd1;
        end else
        if(reset)
        begin
                refresh_counter <= 0;
                refresh_queue <= 4'd0;
        end else
        begin
                refresh_counter <= refresh_counter + 1;
                if(refresh_counter == AVG_REFRESH_DUR)
                begin
                        refresh_counter <= 0;
                        if(refresh_queue != 4'd0)
                                refresh_queue <= refresh_queue - 4'd1;
                end
                if(refresh_queue != 4'd7)
                        refresh_now <= 1;
        end
end
 
endmodule

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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ram/] [ddr/] [ddr_sdram.v] - Blame information for rev 290

Line No.	Rev	Author	Line
1	219	hellwig	`////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Create Date: 02/11/07`
4			`// Last Change: 01/22/12`
5			`// Design Name: DDR SDRAM memory controller`
6			`// Module Name: ddr_sdram`
7			`// Description: memory controller for DDR SDRAM`
8			`// hard coded for 8 Meg x 16 x 4 banks`
9			`//`
10			`// Revision:`
11			`// Revision 0.01 - File Created`
12			`//`
13			`// Development platform: Spartan-3E Starter kit`
14			`//`
15			`// Copyright (C) 2007, Rick Huang`
16			`//`
17			`// Modifications by Hellwig Geisse, 2012`
18			`// - sd_CK_P and sd_CK_N supplied by this module`
19			`// - DDR output registers for sd_CK_P and sd_CK_N added`
20			`// - sd_CLK_O deleted`
21			`// - debug output deleted`
22			`// - burst mode sections of the state machine deleted`
23			`// (have been commented out already)`
24			`// - additional states SD_RD_DONE_1 and SD_WR_DONE_1 inserted`
25			`// (in order to stretch the wACK_O signal, which is to be`
26			`// recognized by external circuits clocked with 50 MHz)`
27			`// - four "write byte" signals added to interface`
28			`// (to allow 8 and 16 bit write operations too)`
29			`// - mask registers UDM_reg_O and LDM_reg_O deleted`
30			`// - DDR output registers for sd_UDM_O and sd_LDM_O added`
31			`// - data_sample_en and its associated multiplexer removed`
32			`// (apparently a debugging vehicle)`
33			`//`
34			`// This library is free software; you can redistribute it and/or`
35			`// modify it under the terms of the GNU Lesser General Public`
36			`// License as published by the Free Software Foundation; either`
37			`// version 2.1 of the License, or (at your option) any later version.`
38			`//`
39			`// This library is distributed in the hope that it will be useful,`
40			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
41			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
42			`// Lesser General Public License for more details.`
43			`//`
44			`// You should have received a copy of the GNU Lesser General Public`
45			`// License along with this library; if not, write to the Free Software`
46			`// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,`
47			`// MA 02110-1301 USA`
48			`//`
49			`////////////////////////////////////////////////////////////////////////////`
50
51	290	hellwig
52			`timescale 1ns/10ps
53			`default_nettype none
54
55
56	219	hellwig	`module ddr_sdram(sd_CK_P, sd_CK_N,`
57			`sd_A_O, sd_BA_O, sd_D_IO,`
58			`sd_RAS_O, sd_CAS_O, sd_WE_O,`
59			`sd_UDM_O, sd_LDM_O,`
60			`sd_UDQS_IO, sd_LDQS_IO,`
61			`sd_CS_O, sd_CKE_O,`
62			`clk0, clk90,`
63			`clk180, clk270,`
64			`reset,`
65			`wADR_I, wSTB_I, wWE_I, wWRB_I,`
66			`wDAT_I, wDAT_O, wACK_O);`
67			`// interface to DDR SDRAM memory`
68			`output sd_CK_P;`
69			`output sd_CK_N;`
70			`output [12:0] sd_A_O;`
71			`output [1:0] sd_BA_O;`
72			`inout [15:0] sd_D_IO;`
73			`output sd_RAS_O;`
74			`output sd_CAS_O;`
75			`output sd_WE_O;`
76			`output sd_UDM_O;`
77			`output sd_LDM_O;`
78			`inout sd_UDQS_IO;`
79			`inout sd_LDQS_IO;`
80			`output sd_CS_O;`
81			`output sd_CKE_O;`
82			`// internal interface signals`
83			`input clk0;`
84			`input clk90;`
85			`input clk180;`
86			`input clk270;`
87			`input reset;`
88			`// A[25:24] = bank[1:0]`
89			`// A[23:11] = row[12:0]`
90			`// A[10: 2] = col[9:1]`
91			`// (a specific combination of the 2+13+9=24 bits adresses`
92			`// a 32-bit word which is transmitted as a burst of two`
93			`// consecutive 16-bit halfwords in one clock cycle)`
94			`input [25:2] wADR_I;`
95			`input wSTB_I;`
96			`input wWE_I;`
97			`input [3:0] wWRB_I;`
98			`input [31:0] wDAT_I;`
99			`output [31:0] wDAT_O;`
100			`output wACK_O;`
101
102			`// Local data storage`
103			`reg [5:0] sd_state;`
104			`reg [3:0] init_state;`
105			`reg [5:0] wait_count;`
106			`reg [14:0] init_wait_count;`
107			`reg [12:0] sd_A_O;`
108			`reg [1:0] sd_BA_O;`
109			`reg [12:0] mode_reg;`
110			`reg sd_RAS_O;`
111			`reg sd_CAS_O;`
112			`reg sd_WE_O;`
113			`reg sd_CS_O;`
114			`reg sd_CKE_O;`
115			`reg wACK_O;`
116
117			`reg [9:0] refresh_counter;`
118			`reg [3:0] refresh_queue; // Number of refresh command to queue`
119			`reg refresh_now;`
120			`reg refresh_ack;`
121
122			`reg [31:0] D_rd_reg;`
123			`reg DQS_state;`
124			`reg DQS_oe; // 1 for output`
125			`reg D_oe; // 1 for output enable`
126
127			`reg [31:0] D_wr_reg; // Data write buffer`
128			`reg [3:0] D_mask_reg; // data mask buffer`
129
130
131			`/***************************************************`
132			`* SD ram clock source`
133			`***************************************************/`
134
135			`ODDR2 #(`
136			`.DDR_ALIGNMENT("NONE"),`
137			`.INIT(1'b0),`
138			`.SRTYPE("SYNC")`
139			`) ODDR2_inst_CK_P (`
140			`.Q(sd_CK_P),`
141			`.C0(clk180),`
142			`.C1(clk0),`
143			`.CE(1'b1),`
144			`.D0(1'b1),`
145			`.D1(1'b0),`
146			`.R(1'b0),`
147			`.S(1'b0)`
148			`);`
149
150			`ODDR2 #(`
151			`.DDR_ALIGNMENT("NONE"),`
152			`.INIT(1'b0),`
153			`.SRTYPE("SYNC")`
154			`) ODDR2_inst_CK_N (`
155			`.Q(sd_CK_N),`
156			`.C0(clk0),`
157			`.C1(clk180),`
158			`.CE(1'b1),`
159			`.D0(1'b1),`
160			`.D1(1'b0),`
161			`.R(1'b0),`
162			`.S(1'b0)`
163			`);`
164
165			`/***************************************************`
166			`* De-duplex of the data path`
167			`* For some reason, for read, the output is CL=2.5, not CL=2`
168			`* Thus, catching of the data is 1/2 a cycle late.`
169			`* Flip the clk0 and clk180, 1/2 cycle delay catched`
170			`* on data_mux_latch`
171			`***************************************************/`
172
173			`// Data from SDRAM will be loaded at {data_mux_out[31:0]}`
174			`wire [31:0] data_mux_out;`
175			`wire [15:0] iddr_conn;`
176			`wire [15:0] oddr_conn;`
177
178
179			`generate`
180			`genvar i;`
181
182			`for(i=0;i<16;i=i+1)`
183			`begin : iou`
184			`IDDR2 #(`
185			`.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"`
186			`.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1`
187			`.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1`
188			`.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset`
189			`) IDDR2_inst (`
190			`.Q0(data_mux_out[i]), // C0 clock`
191			`.Q1(data_mux_out[i+16]), // C1 clock`
192			`.C0(clk180),`
193			`.C1(clk0),`
194			`.CE(1'b1), // Always enabled`
195			`.D(iddr_conn[i]), // 1-bit DDR data input`
196			`.R(1'b0), // 1-bit reset input`
197			`.S(1'b0) // 1-bit set input`
198			`);`
199
200			`ODDR2 #(`
201			`.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"`
202			`.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1`
203			`.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset`
204			`) ODDR2_inst (`
205			`.Q(oddr_conn[i]), // 1-bit DDR output data`
206			`.C0(clk90), // 1-bit clock input`
207			`.C1(clk270), // 1-bit clock input`
208			`.CE(1'b1), // 1-bit clock enable input`
209			`.D0(D_wr_reg[i]), // (associated with C0)`
210			`.D1(D_wr_reg[i+16]), // (associated with C1)`
211			`.R(1'b0), // 1-bit reset input`
212			`.S(1'b0) // 1-bit set input`
213			`);`
214
215			`IOBUF #(`
216			`.DRIVE(4), // Specify the output drive strength`
217			`.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay`
218			`.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8"`
219			`.IOSTANDARD("DEFAULT"), // Specify the I/O standard`
220			`.SLEW("SLOW") // Specify the output slew rate`
221			`) IOBUF_inst (`
222			`.O(iddr_conn[i]), // Buffer output`
223			`.IO(sd_D_IO[i]), // Buffer inout port (connect directly to top-level port)`
224			`.I(oddr_conn[i]), // Buffer input`
225			`.T(~D_oe) // 3-state enable input`
226			`);`
227			`end`
228			`endgenerate`
229
230
231			`wire sd_UDQS_O;`
232			`wire sd_LDQS_O;`
233
234			`ODDR2 #(`
235			`.DDR_ALIGNMENT("NONE"),`
236			`.INIT(1'b0),`
237			`.SRTYPE("SYNC")`
238			`) ODDR2_inst_UDQS (`
239			`.Q(sd_UDQS_O),`
240			`.C0(clk180),`
241			`.C1(clk0),`
242			`.CE(1'b1),`
243			`.D0(DQS_state),`
244			`.D1(1'b0),`
245			`.R(1'b0),`
246			`.S(1'b0)`
247			`);`
248
249			`ODDR2 #(`
250			`.DDR_ALIGNMENT("NONE"),`
251			`.INIT(1'b0),`
252			`.SRTYPE("SYNC")`
253			`) ODDR2_inst_LDQS (`
254			`.Q(sd_LDQS_O),`
255			`.C0(clk180),`
256			`.C1(clk0),`
257			`.CE(1'b1),`
258			`.D0(DQS_state),`
259			`.D1(1'b0),`
260			`.R(1'b0),`
261			`.S(1'b0)`
262			`);`
263
264			`IOBUF #(`
265			`.DRIVE(4),`
266			`.IBUF_DELAY_VALUE("0"),`
267			`.IFD_DELAY_VALUE("AUTO"),`
268			`.IOSTANDARD("DEFAULT"),`
269			`.SLEW("SLOW")`
270			`) IOBUF_inst_UDQS (`
271			`// .O() intentionally not connected`
272			`.IO(sd_UDQS_IO),`
273			`.I(sd_UDQS_O),`
274			`.T(~DQS_oe)`
275			`);`
276
277			`IOBUF #(`
278			`.DRIVE(4),`
279			`.IBUF_DELAY_VALUE("0"),`
280			`.IFD_DELAY_VALUE("AUTO"),`
281			`.IOSTANDARD("DEFAULT"),`
282			`.SLEW("SLOW")`
283			`) IOBUF_inst_LDQS (`
284			`// .O() intentionally not connected`
285			`.IO(sd_LDQS_IO),`
286			`.I(sd_LDQS_O),`
287			`.T(~DQS_oe)`
288			`);`
289
290
291			`reg [31:0] data_mux_latch;`
292			`always @ (posedge clk180)`
293			`begin`
294			`data_mux_latch <= data_mux_out;`
295			`end`
296
297			`/***************************************************`
298			`* Data bus flow direction control`
299			`***************************************************/`
300
301			`assign wDAT_O = D_rd_reg[31:0];`
302
303			`// Mask output`
304
305			`wire UDM_conn;`
306			`wire LDM_conn;`
307
308			`ODDR2 #(`
309			`.DDR_ALIGNMENT("NONE"),`
310			`.INIT(1'b0),`
311			`.SRTYPE("SYNC")`
312			`) ODDR2_inst_UDM (`
313			`.Q(UDM_conn),`
314			`.C0(clk90),`
315			`.C1(clk270),`
316			`.CE(1'b1),`
317			`.D0(~D_mask_reg[1]),`
318			`.D1(~D_mask_reg[3]),`
319			`.R(1'b0),`
320			`.S(1'b0)`
321			`);`
322
323			`ODDR2 #(`
324			`.DDR_ALIGNMENT("NONE"),`
325			`.INIT(1'b0),`
326			`.SRTYPE("SYNC")`
327			`) ODDR2_inst_LDM (`
328			`.Q(LDM_conn),`
329			`.C0(clk90),`
330			`.C1(clk270),`
331			`.CE(1'b1),`
332			`.D0(~D_mask_reg[0]),`
333			`.D1(~D_mask_reg[2]),`
334			`.R(1'b0),`
335			`.S(1'b0)`
336			`);`
337
338			`IOBUF #(`
339			`.DRIVE(4),`
340			`.IBUF_DELAY_VALUE("0"),`
341			`.IFD_DELAY_VALUE("AUTO"),`
342			`.IOSTANDARD("DEFAULT"),`
343			`.SLEW("SLOW")`
344			`) IOBUF_inst_UDM (`
345			`// .O() intentionally not connected`
346			`.IO(sd_UDM_O),`
347			`.I(UDM_conn),`
348			`.T(1'b0)`
349			`);`
350
351			`IOBUF #(`
352			`.DRIVE(4),`
353			`.IBUF_DELAY_VALUE("0"),`
354			`.IFD_DELAY_VALUE("AUTO"),`
355			`.IOSTANDARD("DEFAULT"),`
356			`.SLEW("SLOW")`
357			`) IOBUF_inst_LDM (`
358			`// .O() intentionally not connected`
359			`.IO(sd_LDM_O),`
360			`.I(LDM_conn),`
361			`.T(1'b0)`
362			`);`
363
364
365			`/***************************************************`
366			`* Main tx/rx state machine`
367			`***************************************************/`
368
369			`/* Timing */`
370			`parameter WAIT_TIME = 5'd5;`
371			`parameter INIT_WAIT = 15'h3000;`
372			`parameter INIT_CLK_EN_WAIT = 15'h10;`
373			`parameter WAIT_CMD_MAX = 6'b100000;`
374			`parameter REFRESH_WAIT = WAIT_CMD_MAX - 6'd7;`
375			`parameter ACCESS_WAIT = WAIT_CMD_MAX - 6'd1;`
376			`parameter CAS_WAIT = WAIT_CMD_MAX - 6'd3;`
377			`parameter AVG_REFRESH_DUR = 10'd700;`
378
379			`/* Main state machine */`
380			`parameter SD_IDLE = 0,`
381			`SD_INIT = 1,`
382			`SD_INIT_WAIT = 2,`
383			`SD_PRECHG_ALL = 3,`
384			`SD_PRECHG_ALL1 = 4,`
385			`SD_AUTO_REF = 5,`
386			`SD_AUTO_REF1 = 6,`
387			`SD_AUTO_REF_ACK = 7,`
388			`SD_LD_MODE = 8,`
389			`SD_LD_MODE1 = 9,`
390			`SD_RD_START = 10,`
391			`SD_RD_COL = 11,`
392			`SD_RD_CAS_WAIT = 12,`
393			`SD_RD_LATCH = 13,`
394			`SD_RD_LATCH1 = 14,`
395			`SD_RD_DONE = 15,`
396			`SD_WR_START = 16,`
397			`SD_WR_COL = 17,`
398			`SD_WR_CAS_WAIT = 18,`
399			`SD_WR_LATCH = 19,`
400			`SD_WR_LATCH1 = 20,`
401			`SD_WR_DONE = 21,`
402			`SD_RD_DONE_1 = 22,`
403			`SD_WR_DONE_1 = 23;`
404
405			`/* Initialization state machine */`
406			`parameter SI_START = 0,`
407			`SI_PRECHG = 1,`
408			`SI_LOAD_EX_MODE = 2,`
409			`SI_LOAD_MODE = 3,`
410			`SI_LOAD_MODE2 = 4,`
411			`SI_PRECHG2 = 5,`
412			`SI_AUTO_REF = 6,`
413			`SI_AUTO_REF2 = 7,`
414			`SI_DONE = 8;`
415
416
417			`always @ (posedge clk0)`
418			`begin`
419			`if(reset)`
420			`begin`
421			`sd_state <= SD_INIT;`
422			`init_state <= SI_START;`
423			`end else`
424			`begin`
425			`wait_count <= wait_count + 1;`
426
427			`case (sd_state)`
428			`SD_INIT: // Initialize, wait until INIT_WAIT`
429			`begin`
430			`case (init_state)`
431			`SI_START:`
432			`begin`
433			`sd_state <= SD_INIT_WAIT;`
434			`init_state <= SI_PRECHG;`
435			`sd_RAS_O <= 1;`
436			`sd_CAS_O <= 1;`
437			`sd_WE_O <= 1;`
438			`sd_CS_O <= 1;`
439			`sd_CKE_O <= 0;`
440			`init_wait_count <= 16'd0;`
441			`end`
442			`SI_PRECHG:`
443			`begin`
444			`sd_state <= SD_PRECHG_ALL;`
445			`init_state <= SI_LOAD_EX_MODE;`
446			`end`
447			`SI_LOAD_EX_MODE:`
448			`begin`
449			`// Normal operation`
450			`mode_reg <= 13'b0000000000000;`
451			`sd_BA_O <= 2'b01;`
452			`sd_state <= SD_LD_MODE;`
453			`init_state <= SI_LOAD_MODE;`
454			`end`
455			`SI_LOAD_MODE:`
456			`begin`
457			`// CAS = 2, Reset DLL, Burst = 2, sequential`
458			`mode_reg <= {6'b000010, 3'b010, 1'b0, 3'b001};`
459			`sd_BA_O <= 2'b00;`
460			`sd_state <= SD_LD_MODE;`
461			`init_state <= SI_LOAD_MODE2;`
462			`end`
463			`SI_LOAD_MODE2:`
464			`begin`
465			`// CAS = 2, NO Reset DLL, Burst = 2, sequential`
466			`mode_reg <= {6'b000000, 3'b010, 1'b0, 3'b001};`
467			`sd_BA_O <= 2'b00;`
468			`sd_state <= SD_LD_MODE;`
469			`init_state <= SI_PRECHG2;`
470			`end`
471			`SI_PRECHG2:`
472			`begin`
473			`sd_state <= SD_PRECHG_ALL;`
474			`init_state <= SI_AUTO_REF;`
475			`end`
476			`SI_AUTO_REF:`
477			`begin`
478			`sd_state <= SD_AUTO_REF;`
479			`init_state <= SI_AUTO_REF2;`
480			`end`
481			`SI_AUTO_REF2:`
482			`begin`
483			`sd_state <= SD_AUTO_REF;`
484			`init_state <= SI_DONE;`
485			`end`
486			`SI_DONE:`
487			`begin`
488			`init_state <= SI_DONE;`
489			`sd_state <= SD_IDLE;`
490			`end`
491			`default:`
492			`init_state <= SI_START;`
493			`endcase`
494			`end`
495			`// Waiting for SDRAM waking up ***************************`
496			`SD_INIT_WAIT:`
497			`begin`
498			`init_wait_count <= init_wait_count + 1;`
499			`if(init_wait_count == INIT_WAIT)`
500			`begin`
501			`sd_state <= SD_INIT;`
502			`end`
503			`if(init_wait_count == INIT_CLK_EN_WAIT)`
504			`begin`
505			`sd_CKE_O <= 1; // Wake up the SDRAM`
506			`end`
507			`end`
508			`// Precharge command *************************************`
509			`SD_PRECHG_ALL:`
510			`begin`
511			`sd_state <= SD_PRECHG_ALL1;`
512			`sd_RAS_O <= 0;`
513			`sd_CAS_O <= 1;`
514			`sd_WE_O <= 0;`
515			`sd_CS_O <= 0;`
516			`sd_A_O[10] <= 1; // Command for precharge all`
517			`end`
518			`SD_PRECHG_ALL1:`
519			`begin`
520			`sd_CS_O <= 1;`
521			`sd_RAS_O <= 1;`
522			`sd_CAS_O <= 1;`
523			`sd_WE_O <= 1;`
524			`sd_state <= SD_IDLE; // Precharge takes 15nS before next command`
525			`end`
526			`// Load mode register ************************************`
527			`SD_LD_MODE:`
528			`begin`
529			`sd_state <= SD_LD_MODE1;`
530			`sd_RAS_O <= 0;`
531			`sd_CAS_O <= 0;`
532			`sd_WE_O <= 0;`
533			`sd_CS_O <= 0;`
534			`sd_A_O[12:0] <= mode_reg;`
535			`end`
536			`SD_LD_MODE1:`
537			`begin`
538			`sd_CS_O <= 1;`
539			`sd_RAS_O <= 1;`
540			`sd_CAS_O <= 1;`
541			`sd_WE_O <= 1; // Load Mode takes 12nS`
542			`sd_state <= SD_IDLE; // Add wait if needed`
543			`end`
544			`// Auto refresh command **********************************`
545			`SD_AUTO_REF:`
546			`begin`
547			`sd_state <= SD_AUTO_REF1;`
548			`sd_RAS_O <= 0;`
549			`sd_CAS_O <= 0;`
550			`sd_WE_O <= 1;`
551			`sd_CS_O <= 0;`
552			`wait_count <= REFRESH_WAIT;`
553			`end`
554			`SD_AUTO_REF1:`
555			`begin`
556			`sd_CS_O <= 1; // Issue NOP during wait`
557			`sd_RAS_O <= 1;`
558			`sd_CAS_O <= 1;`
559			`sd_WE_O <= 1;`
560			`if(wait_count[5] == 1) // Time up, return to idle`
561			`begin`
562			`sd_state <= SD_AUTO_REF_ACK;`
563			`refresh_ack <= 1;`
564			`end`
565			`end`
566			`SD_AUTO_REF_ACK: // Interlocking state`
567			`begin`
568			`sd_state <= SD_IDLE;`
569			`refresh_ack <= 0;`
570			`end`
571			`// Read cycle ********************************************`
572			`SD_RD_START:`
573			`begin`
574			`sd_state <= SD_RD_COL;`
575			`sd_RAS_O <= 0;`
576			`sd_CAS_O <= 1;`
577			`sd_WE_O <= 1;`
578			`sd_CS_O <= 0;`
579			`sd_BA_O[1:0] <= wADR_I[25:24];`
580			`sd_A_O[12:0] <= wADR_I[23:11];`
581			`wait_count <= ACCESS_WAIT;`
582			`D_oe <= 0; // Not driving the bus`
583			`DQS_state <= 0;`
584			`end`
585			`SD_RD_COL:`
586			`begin`
587			`if(wait_count[5] != 1)`
588			`begin`
589			`sd_CS_O <= 1; // NOP command during access wait`
590			`sd_RAS_O <= 1;`
591			`sd_CAS_O <= 1;`
592			`sd_WE_O <= 1;`
593			`end else`
594			`begin`
595			`sd_CS_O <= 0; // Access column`
596			`sd_RAS_O <= 1;`
597			`sd_CAS_O <= 0;`
598			`sd_WE_O <= 1;`
599			`sd_state <= SD_RD_CAS_WAIT;`
600			`sd_A_O[9:1] <= wADR_I[10:2];`
601			`sd_A_O[10] <= 1; // Use auto-precharge`
602			`sd_A_O[0] <= 0;`
603			`wait_count <= CAS_WAIT;`
604			`DQS_oe <= 0; // Set DQS for input`
605			`end`
606			`end`
607			`SD_RD_CAS_WAIT:`
608			`begin // Wait until DQS signal there is data`
609			`if(wait_count[5] != 1)`
610			`begin`
611			`sd_CS_O <= 1; // NOP command during access wait`
612			`sd_RAS_O <= 1;`
613			`sd_CAS_O <= 1;`
614			`sd_WE_O <= 1;`
615			`end else`
616			`begin`
617			`sd_state <= SD_RD_LATCH;`
618			`end`
619			`end`
620			`SD_RD_LATCH:`
621			`begin`
622			`D_rd_reg <= data_mux_latch[31:0];`
623			`wACK_O <= 1;`
624			`sd_state <= SD_RD_DONE;`
625			`end`
626			`SD_RD_DONE:`
627			`begin`
628			`wACK_O <= 1;`
629			`sd_state <= SD_RD_DONE_1;`
630			`DQS_state <= 0;`
631			`DQS_oe <= 1; // Set DQS back to output`
632			`end`
633			`SD_RD_DONE_1:`
634			`begin`
635			`wACK_O <= 0;`
636			`sd_state <= SD_IDLE;`
637			`end`
638			`// Write cycle *******************************************`
639			`SD_WR_START:`
640			`begin // Open the bank - ACTIVE command`
641			`sd_state <= SD_WR_COL;`
642			`sd_RAS_O <= 0;`
643			`sd_CAS_O <= 1;`
644			`sd_WE_O <= 1;`
645			`sd_CS_O <= 0;`
646			`sd_BA_O[1:0] <= wADR_I[25:24];`
647			`sd_A_O[12:0] <= wADR_I[23:11];`
648			`D_wr_reg <= wDAT_I;`
649			`D_mask_reg <= wWRB_I;`
650			`wait_count <= ACCESS_WAIT;`
651			`DQS_state <= 0;`
652			`end`
653			`SD_WR_COL:`
654			`begin`
655			`if(wait_count[5] != 1)`
656			`begin`
657			`sd_CS_O <= 1; // NOP command during access wait`
658			`sd_RAS_O <= 1;`
659			`sd_CAS_O <= 1;`
660			`sd_WE_O <= 1;`
661			`end else`
662			`begin`
663			`sd_CS_O <= 0; // Access column`
664			`sd_RAS_O <= 1;`
665			`sd_CAS_O <= 0;`
666			`sd_WE_O <= 0;`
667			`DQS_oe <= 1;`
668			`sd_state <= SD_WR_CAS_WAIT;`
669			`sd_A_O[9:1] <= wADR_I[10:2];`
670			`sd_A_O[10] <= 1; // Use auto-precharge`
671			`sd_A_O[0] <= 0;`
672			`end`
673			`end`
674			`SD_WR_CAS_WAIT:`
675			`begin // Wait until DQS signal there is data`
676			`sd_state <= SD_WR_LATCH;`
677			`DQS_state <= 1; // Start with DQS low`
678			`D_oe <= 1; // Drive the data bus`
679			`sd_CS_O <= 1;`
680			`sd_RAS_O <= 1;`
681			`sd_CAS_O <= 1;`
682			`sd_WE_O <= 1;`
683			`end`
684			`SD_WR_LATCH:`
685			`begin`
686			`sd_state <= SD_WR_LATCH1;`
687			`DQS_state <= 0;`
688			`end`
689			`SD_WR_LATCH1:`
690			`begin`
691			`sd_state <= SD_WR_DONE;`
692			`DQS_state <= 0;`
693			`wACK_O <= 1;`
694			`end`
695			`SD_WR_DONE:`
696			`begin`
697			`D_oe <= 0;`
698			`wACK_O <= 1;`
699			`sd_state <= SD_WR_DONE_1;`
700			`end`
701			`SD_WR_DONE_1:`
702			`begin`
703			`wACK_O <= 0;`
704			`sd_state <= SD_IDLE;`
705			`end`
706			`// Wishbone transfer is done during idle time`
707			`SD_IDLE: /* Idle/sleep process */`
708			`begin`
709			`sd_RAS_O <= 1; // Set for NOP by default`
710			`sd_CAS_O <= 1;`
711			`sd_WE_O <= 1;`
712			`sd_CS_O <= 1;`
713			`if(init_state != SI_DONE) // If still in init cycle, go back and work`
714			`sd_state <= SD_INIT;`
715			`else if(wSTB_I && !wWE_I) // Start of a read command`
716			`sd_state <= SD_RD_START;`
717			`else if(wSTB_I && wWE_I) // Start of a write command`
718			`sd_state <= SD_WR_START;`
719			`else if(refresh_now) // Refresh is the last command`
720			`sd_state <= SD_AUTO_REF;`
721			`end`
722
723			`default:`
724			`sd_state <= SD_IDLE;`
725			`endcase`
726			`end`
727			`end`
728
729			`/* Seperate always block for refresh timer */`
730			`/* The idea is to queue as many as 8 refresh command as possible if the bus is`
731			`* free */`
732			`always @ (posedge clk0)`
733			`begin`
734			`if(refresh_ack)`
735			`begin`
736			`refresh_now <= 0;`
737			`refresh_queue <= refresh_queue + 4'd1;`
738			`end else`
739			`if(reset)`
740			`begin`
741			`refresh_counter <= 0;`
742			`refresh_queue <= 4'd0;`
743			`end else`
744			`begin`
745			`refresh_counter <= refresh_counter + 1;`
746			`if(refresh_counter == AVG_REFRESH_DUR)`
747			`begin`
748			`refresh_counter <= 0;`
749			`if(refresh_queue != 4'd0)`
750			`refresh_queue <= refresh_queue - 4'd1;`
751			`end`
752			`if(refresh_queue != 4'd7)`
753			`refresh_now <= 1;`
754			`end`
755			`end`
756
757			`endmodule`