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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ram/] [sdr/] [ram.v] - Blame information for rev 119

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//
// ram.v -- main memory, using SDRAM
//
 
 
module ram(clk, clk_ok, reset,
           en, wr, size, addr,
           data_in, data_out, wt,
           sdram_cke, sdram_cs_n,
           sdram_udqm, sdram_ldqm,
           sdram_ras_n, sdram_cas_n,
           sdram_we_n, sdram_ba,
           sdram_a, sdram_dq);
    // internal interface signals
    input clk;
    input clk_ok;
    input reset;
    input en;
    input wr;
    input [1:0] size;
    input [24:0] addr;
    input [31:0] data_in;
    output reg [31:0] data_out;
    output reg wt;
    // SDRAM interface signals
    output sdram_cke;
    output sdram_cs_n;
    output sdram_udqm;
    output sdram_ldqm;
    output sdram_ras_n;
    output sdram_cas_n;
    output sdram_we_n;
    output [1:0] sdram_ba;
    output [12:0] sdram_a;
    inout [15:0] sdram_dq;
 
  reg [3:0] state;
  reg a0;
  reg cntl_read;
  reg cntl_write;
  wire cntl_done;
  wire [23:0] cntl_addr;
  reg [15:0] cntl_din;
  wire [15:0] cntl_dout;
 
  wire sd_out_en;
  wire [15:0] sd_out;
 
//--------------------------------------------------------------
 
  sdramCntl sdramCntl1(
    // clock
    .clk(clk),
    .clk_ok(clk_ok),
    // host side
    .rd(cntl_read & ~cntl_done),
    .wr(cntl_write & ~cntl_done),
    .done(cntl_done),
    .hAddr(cntl_addr),
    .hDIn(cntl_din),
    .hDOut(cntl_dout),
    // SDRAM side
    .cke(sdram_cke),
    .ce_n(sdram_cs_n),
    .ras_n(sdram_ras_n),
    .cas_n(sdram_cas_n),
    .we_n(sdram_we_n),
    .ba(sdram_ba),
    .sAddr(sdram_a),
    .sDIn(sdram_dq),
    .sDOut(sd_out),
    .sDOutEn(sd_out_en),
    .dqmh(sdram_udqm),
    .dqml(sdram_ldqm)
  );
 
  assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz;
 
//--------------------------------------------------------------
 
  // the SDRAM is organized in 16-bit halfwords
  // address line 0 is controlled by the state machine
  // (this is necessary for word accesses)
  assign cntl_addr[23:1] = addr[24:2];
  assign cntl_addr[0] = a0;
 
  // state machine for SDRAM access
  always @(posedge clk) begin
    if (reset == 1) begin
      state <= 4'b0000;
      wt <= 1;
    end else begin
      case (state)
        4'b0000:
          // wait for access
          begin
            if (en == 1) begin
              // access
              if (wr == 1) begin
                // write
                if (size[1] == 1) begin
                  // write word
                  state <= 4'b0001;
                end else begin
                  if (size[0] == 1) begin
                    // write halfword
                    state <= 4'b0101;
                  end else begin
                    // write byte
                    state <= 4'b0111;
                  end
                end
              end else begin
                // read
                if (size[1] == 1) begin
                  // read word
                  state <= 4'b0011;
                end else begin
                  if (size[0] == 1) begin
                    // read halfword
                    state <= 4'b0110;
                  end else begin
                    // read byte
                    state <= 4'b1001;
                  end
                end
              end
            end
          end
        4'b0001:
          // write word, upper 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b0010;
            end
          end
        4'b0010:
          // write word, lower 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              wt <= 0;
            end
          end
        4'b0011:
          // read word, upper 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b0100;
              data_out[31:16] <= cntl_dout;
            end
          end
        4'b0100:
          // read word, lower 16 bits
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              data_out[15:0] <= cntl_dout;
              wt <= 0;
            end
          end
        4'b0101:
          // write halfword
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              wt <= 0;
            end
          end
        4'b0110:
          // read halfword
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              data_out[31:16] <= 16'h0000;
              data_out[15:0] <= cntl_dout;
              wt <= 0;
            end
          end
        4'b0111:
          // write byte (read halfword cycle)
          begin
            if (cntl_done == 1) begin
              state <= 4'b1000;
              data_out[31:16] <= 16'h0000;
              data_out[15:0] <= cntl_dout;
            end
          end
        4'b1000:
          // write byte (write halfword cycle)
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              wt <= 0;
            end
          end
        4'b1001:
          // read byte
          begin
            if (cntl_done == 1) begin
              state <= 4'b1111;
              data_out[31:8] <= 24'h000000;
              if (addr[0] == 0) begin
                data_out[7:0] <= cntl_dout[15:8];
              end else begin
                data_out[7:0] <= cntl_dout[7:0];
              end
              wt <= 0;
            end
          end
        4'b1111:
          // end of bus cycle
          begin
            state <= 4'b0000;
            wt <= 1;
          end
        default:
          // all other states: reset
          begin
            state <= 4'b0000;
            wt <= 1;
          end
      endcase
    end
  end
 
  // output of state machine
  always @(*) begin
    case (state)
      4'b0000:
        // wait for access
        begin
          a0 = 1'bx;
          cntl_read = 0;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0001:
        // write word, upper 16 bits
        begin
          a0 = 1'b0;
          cntl_read = 0;
          cntl_write = 1;
          cntl_din = data_in[31:16];
        end
      4'b0010:
        // write word, lower 16 bits
        begin
          a0 = 1'b1;
          cntl_read = 0;
          cntl_write = 1;
          cntl_din = data_in[15:0];
        end
      4'b0011:
        // read word, upper 16 bits
        begin
          a0 = 1'b0;
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0100:
        // read word, lower 16 bits
        begin
          a0 = 1'b1;
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0101:
        // write halfword
        begin
          a0 = addr[1];
          cntl_read = 0;
          cntl_write = 1;
          cntl_din = data_in[15:0];
        end
      4'b0110:
        // read halfword
        begin
          a0 = addr[1];
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b0111:
        // write byte (read halfword cycle)
        begin
          a0 = addr[1];
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b1000:
        // write byte (write halfword cycle)
        begin
          a0 = addr[1];
          cntl_read = 0;
          cntl_write = 1;
          if (addr[0] == 0) begin
            cntl_din = { data_in[7:0], data_out[7:0] };
          end else begin
            cntl_din = { data_out[15:8], data_in[7:0] };
          end
        end
      4'b1001:
        // read byte
        begin
          a0 = addr[1];
          cntl_read = 1;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      4'b1111:
        // end of bus cycle
        begin
          a0 = 1'bx;
          cntl_read = 0;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
      default:
        // all other states: reset
        begin
          a0 = 1'bx;
          cntl_read = 0;
          cntl_write = 0;
          cntl_din = 16'hxxxx;
        end
    endcase
  end
 
endmodule

Line No.	Rev	Author	Line
1	119	hellwig	`//`
2			`// ram.v -- main memory, using SDRAM`
3			`//`
4
5
6	27	hellwig	`module ram(clk, clk_ok, reset,`
7			`en, wr, size, addr,`
8			`data_in, data_out, wt,`
9			`sdram_cke, sdram_cs_n,`
10			`sdram_udqm, sdram_ldqm,`
11			`sdram_ras_n, sdram_cas_n,`
12			`sdram_we_n, sdram_ba,`
13			`sdram_a, sdram_dq);`
14	119	hellwig	`// internal interface signals`
15	27	hellwig	`input clk;`
16			`input clk_ok;`
17			`input reset;`
18			`input en;`
19			`input wr;`
20			`input [1:0] size;`
21			`input [24:0] addr;`
22			`input [31:0] data_in;`
23			`output reg [31:0] data_out;`
24			`output reg wt;`
25	119	hellwig	`// SDRAM interface signals`
26	27	hellwig	`output sdram_cke;`
27			`output sdram_cs_n;`
28			`output sdram_udqm;`
29			`output sdram_ldqm;`
30			`output sdram_ras_n;`
31			`output sdram_cas_n;`
32			`output sdram_we_n;`
33			`output [1:0] sdram_ba;`
34			`output [12:0] sdram_a;`
35			`inout [15:0] sdram_dq;`
36
37			`reg [3:0] state;`
38			`reg a0;`
39			`reg cntl_read;`
40			`reg cntl_write;`
41			`wire cntl_done;`
42			`wire [23:0] cntl_addr;`
43			`reg [15:0] cntl_din;`
44			`wire [15:0] cntl_dout;`
45
46			`wire sd_out_en;`
47			`wire [15:0] sd_out;`
48
49			`//--------------------------------------------------------------`
50
51			`sdramCntl sdramCntl1(`
52			`// clock`
53			`.clk(clk),`
54			`.clk_ok(clk_ok),`
55			`// host side`
56			`.rd(cntl_read & ~cntl_done),`
57			`.wr(cntl_write & ~cntl_done),`
58			`.done(cntl_done),`
59			`.hAddr(cntl_addr),`
60			`.hDIn(cntl_din),`
61			`.hDOut(cntl_dout),`
62			`// SDRAM side`
63			`.cke(sdram_cke),`
64			`.ce_n(sdram_cs_n),`
65			`.ras_n(sdram_ras_n),`
66			`.cas_n(sdram_cas_n),`
67			`.we_n(sdram_we_n),`
68			`.ba(sdram_ba),`
69			`.sAddr(sdram_a),`
70			`.sDIn(sdram_dq),`
71			`.sDOut(sd_out),`
72			`.sDOutEn(sd_out_en),`
73			`.dqmh(sdram_udqm),`
74			`.dqml(sdram_ldqm)`
75			`);`
76
77			`assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz;`
78
79			`//--------------------------------------------------------------`
80
81			`// the SDRAM is organized in 16-bit halfwords`
82			`// address line 0 is controlled by the state machine`
83	119	hellwig	`// (this is necessary for word accesses)`
84	27	hellwig	`assign cntl_addr[23:1] = addr[24:2];`
85			`assign cntl_addr[0] = a0;`
86
87			`// state machine for SDRAM access`
88			`always @(posedge clk) begin`
89			`if (reset == 1) begin`
90			`state <= 4'b0000;`
91			`wt <= 1;`
92			`end else begin`
93			`case (state)`
94			`4'b0000:`
95			`// wait for access`
96			`begin`
97			`if (en == 1) begin`
98			`// access`
99			`if (wr == 1) begin`
100			`// write`
101			`if (size[1] == 1) begin`
102			`// write word`
103			`state <= 4'b0001;`
104			`end else begin`
105			`if (size[0] == 1) begin`
106			`// write halfword`
107			`state <= 4'b0101;`
108			`end else begin`
109			`// write byte`
110			`state <= 4'b0111;`
111			`end`
112			`end`
113			`end else begin`
114			`// read`
115			`if (size[1] == 1) begin`
116			`// read word`
117			`state <= 4'b0011;`
118			`end else begin`
119			`if (size[0] == 1) begin`
120			`// read halfword`
121			`state <= 4'b0110;`
122			`end else begin`
123			`// read byte`
124			`state <= 4'b1001;`
125			`end`
126			`end`
127			`end`
128			`end`
129			`end`
130			`4'b0001:`
131			`// write word, upper 16 bits`
132			`begin`
133			`if (cntl_done == 1) begin`
134			`state <= 4'b0010;`
135			`end`
136			`end`
137			`4'b0010:`
138			`// write word, lower 16 bits`
139			`begin`
140			`if (cntl_done == 1) begin`
141			`state <= 4'b1111;`
142			`wt <= 0;`
143			`end`
144			`end`
145			`4'b0011:`
146			`// read word, upper 16 bits`
147			`begin`
148			`if (cntl_done == 1) begin`
149			`state <= 4'b0100;`
150			`data_out[31:16] <= cntl_dout;`
151			`end`
152			`end`
153			`4'b0100:`
154			`// read word, lower 16 bits`
155			`begin`
156			`if (cntl_done == 1) begin`
157			`state <= 4'b1111;`
158			`data_out[15:0] <= cntl_dout;`
159			`wt <= 0;`
160			`end`
161			`end`
162			`4'b0101:`
163			`// write halfword`
164			`begin`
165			`if (cntl_done == 1) begin`
166			`state <= 4'b1111;`
167			`wt <= 0;`
168			`end`
169			`end`
170			`4'b0110:`
171			`// read halfword`
172			`begin`
173			`if (cntl_done == 1) begin`
174			`state <= 4'b1111;`
175			`data_out[31:16] <= 16'h0000;`
176			`data_out[15:0] <= cntl_dout;`
177			`wt <= 0;`
178			`end`
179			`end`
180			`4'b0111:`
181			`// write byte (read halfword cycle)`
182			`begin`
183			`if (cntl_done == 1) begin`
184			`state <= 4'b1000;`
185			`data_out[31:16] <= 16'h0000;`
186			`data_out[15:0] <= cntl_dout;`
187			`end`
188			`end`
189			`4'b1000:`
190			`// write byte (write halfword cycle)`
191			`begin`
192			`if (cntl_done == 1) begin`
193			`state <= 4'b1111;`
194			`wt <= 0;`
195			`end`
196			`end`
197			`4'b1001:`
198			`// read byte`
199			`begin`
200			`if (cntl_done == 1) begin`
201			`state <= 4'b1111;`
202			`data_out[31:8] <= 24'h000000;`
203			`if (addr[0] == 0) begin`
204			`data_out[7:0] <= cntl_dout[15:8];`
205			`end else begin`
206			`data_out[7:0] <= cntl_dout[7:0];`
207			`end`
208			`wt <= 0;`
209			`end`
210			`end`
211			`4'b1111:`
212			`// end of bus cycle`
213			`begin`
214			`state <= 4'b0000;`
215			`wt <= 1;`
216			`end`
217			`default:`
218			`// all other states: reset`
219			`begin`
220			`state <= 4'b0000;`
221			`wt <= 1;`
222			`end`
223			`endcase`
224			`end`
225			`end`
226
227			`// output of state machine`
228			`always @(*) begin`
229			`case (state)`
230			`4'b0000:`
231			`// wait for access`
232			`begin`
233			`a0 = 1'bx;`
234			`cntl_read = 0;`
235			`cntl_write = 0;`
236			`cntl_din = 16'hxxxx;`
237			`end`
238			`4'b0001:`
239			`// write word, upper 16 bits`
240			`begin`
241			`a0 = 1'b0;`
242			`cntl_read = 0;`
243			`cntl_write = 1;`
244			`cntl_din = data_in[31:16];`
245			`end`
246			`4'b0010:`
247			`// write word, lower 16 bits`
248			`begin`
249			`a0 = 1'b1;`
250			`cntl_read = 0;`
251			`cntl_write = 1;`
252			`cntl_din = data_in[15:0];`
253			`end`
254			`4'b0011:`
255			`// read word, upper 16 bits`
256			`begin`
257			`a0 = 1'b0;`
258			`cntl_read = 1;`
259			`cntl_write = 0;`
260			`cntl_din = 16'hxxxx;`
261			`end`
262			`4'b0100:`
263			`// read word, lower 16 bits`
264			`begin`
265			`a0 = 1'b1;`
266			`cntl_read = 1;`
267			`cntl_write = 0;`
268			`cntl_din = 16'hxxxx;`
269			`end`
270			`4'b0101:`
271			`// write halfword`
272			`begin`
273			`a0 = addr[1];`
274			`cntl_read = 0;`
275			`cntl_write = 1;`
276			`cntl_din = data_in[15:0];`
277			`end`
278			`4'b0110:`
279			`// read halfword`
280			`begin`
281			`a0 = addr[1];`
282			`cntl_read = 1;`
283			`cntl_write = 0;`
284			`cntl_din = 16'hxxxx;`
285			`end`
286			`4'b0111:`
287			`// write byte (read halfword cycle)`
288			`begin`
289			`a0 = addr[1];`
290			`cntl_read = 1;`
291			`cntl_write = 0;`
292			`cntl_din = 16'hxxxx;`
293			`end`
294			`4'b1000:`
295			`// write byte (write halfword cycle)`
296			`begin`
297			`a0 = addr[1];`
298			`cntl_read = 0;`
299			`cntl_write = 1;`
300			`if (addr[0] == 0) begin`
301			`cntl_din = { data_in[7:0], data_out[7:0] };`
302			`end else begin`
303			`cntl_din = { data_out[15:8], data_in[7:0] };`
304			`end`
305			`end`
306			`4'b1001:`
307			`// read byte`
308			`begin`
309			`a0 = addr[1];`
310			`cntl_read = 1;`
311			`cntl_write = 0;`
312			`cntl_din = 16'hxxxx;`
313			`end`
314			`4'b1111:`
315			`// end of bus cycle`
316			`begin`
317			`a0 = 1'bx;`
318			`cntl_read = 0;`
319			`cntl_write = 0;`
320			`cntl_din = 16'hxxxx;`
321			`end`
322			`default:`
323			`// all other states: reset`
324			`begin`
325			`a0 = 1'bx;`
326			`cntl_read = 0;`
327			`cntl_write = 0;`
328			`cntl_din = 16'hxxxx;`
329			`end`
330			`endcase`
331			`end`
332
333			`endmodule`

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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ram/] [sdr/] [ram.v] - Blame information for rev 119