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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ser/] [rcv.v] - Blame information for rev 314

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Line No. Rev Author Line
1 117 hellwig
//
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// rcv.v -- serial line receiver
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//
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6 290 hellwig
`timescale 1ns/10ps
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`default_nettype none
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10 27 hellwig
module rcv(clk, reset, full, parallel_out, serial_in);
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    input clk;
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    input reset;
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    output reg full;
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    output [7:0] parallel_out;
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    input serial_in;
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  reg serial_p;
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  reg serial_s;
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  reg [3:0] state;
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  reg [8:0] shift;
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  reg [10:0] count;
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  assign parallel_out[7:0] = shift[7:0];
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  always @(posedge clk) begin
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    serial_p <= serial_in;
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    serial_s <= serial_p;
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  end
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  always @(posedge clk) begin
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    if (reset == 1) begin
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      state <= 4'h0;
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      full <= 0;
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    end else begin
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      if (state == 4'h0) begin
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        full <= 0;
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        if (serial_s == 0) begin
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          state <= 4'h1;
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          count <= 651;
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        end
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      end else
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      if (state == 4'hb) begin
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        state <= 4'h0;
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        full <= 1;
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      end else begin
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        if (count == 0) begin
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          state <= state + 1;
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          shift[8:0] <= { serial_s, shift[8:1] };
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          count <= 1302;
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        end else begin
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          count <= count - 1;
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        end
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      end
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    end
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  end
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endmodule

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