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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ser/] [xmtbuf.v] - Blame information for rev 333

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//
// xmtbuf.v -- serial line transmitter buffer
//
 
 
`timescale 1ns/10ps
`default_nettype none
 
 
module xmtbuf(clk, reset, write, ready, data_in, serial_out);
    input clk;
    input reset;
    input write;
    output reg ready;
    input [7:0] data_in;
    output serial_out;
 
  reg [1:0] state;
  reg [7:0] data_hold;
  reg load;
  wire empty;
 
  xmt xmt_1(clk, reset, load, empty, data_hold, serial_out);
 
  always @(posedge clk) begin
    if (reset == 1) begin
      state <= 2'b00;
      ready <= 1;
      load <= 0;
    end else begin
      case (state)
        2'b00:
          begin
            if (write == 1) begin
              state <= 2'b01;
              data_hold <= data_in;
              ready <= 0;
              load <= 1;
            end
          end
        2'b01:
          begin
            state <= 2'b10;
            ready <= 1;
            load <= 0;
          end
        2'b10:
          begin
            if (empty == 1 && write == 0) begin
              state <= 2'b00;
              ready <= 1;
              load <= 0;
            end else
            if (empty == 1 && write == 1) begin
              state <= 2'b01;
              data_hold <= data_in;
              ready <= 0;
              load <= 1;
            end else
            if (empty == 0 && write == 1) begin
              state <= 2'b11;
              data_hold <= data_in;
              ready <= 0;
              load <= 0;
            end
          end
        2'b11:
          begin
            if (empty == 1) begin
              state <= 2'b01;
              ready <= 0;
              load <= 1;
            end
          end
      endcase
    end
  end
 
endmodule

Line No.	Rev	Author	Line
1	117	hellwig	`//`
2			`// xmtbuf.v -- serial line transmitter buffer`
3			`//`
4
5
6	290	hellwig	`timescale 1ns/10ps
7			`default_nettype none
8
9
10	27	hellwig	`module xmtbuf(clk, reset, write, ready, data_in, serial_out);`
11			`input clk;`
12			`input reset;`
13			`input write;`
14			`output reg ready;`
15			`input [7:0] data_in;`
16			`output serial_out;`
17
18			`reg [1:0] state;`
19			`reg [7:0] data_hold;`
20			`reg load;`
21			`wire empty;`
22
23	290	hellwig	`xmt xmt_1(clk, reset, load, empty, data_hold, serial_out);`
24	27	hellwig
25			`always @(posedge clk) begin`
26			`if (reset == 1) begin`
27			`state <= 2'b00;`
28			`ready <= 1;`
29			`load <= 0;`
30			`end else begin`
31			`case (state)`
32			`2'b00:`
33			`begin`
34			`if (write == 1) begin`
35			`state <= 2'b01;`
36			`data_hold <= data_in;`
37			`ready <= 0;`
38			`load <= 1;`
39			`end`
40			`end`
41			`2'b01:`
42			`begin`
43			`state <= 2'b10;`
44			`ready <= 1;`
45			`load <= 0;`
46			`end`
47			`2'b10:`
48			`begin`
49			`if (empty == 1 && write == 0) begin`
50			`state <= 2'b00;`
51			`ready <= 1;`
52			`load <= 0;`
53			`end else`
54			`if (empty == 1 && write == 1) begin`
55			`state <= 2'b01;`
56			`data_hold <= data_in;`
57			`ready <= 0;`
58			`load <= 1;`
59			`end else`
60			`if (empty == 0 && write == 1) begin`
61			`state <= 2'b11;`
62			`data_hold <= data_in;`
63			`ready <= 0;`
64			`load <= 0;`
65			`end`
66			`end`
67			`2'b11:`
68			`begin`
69			`if (empty == 1) begin`
70			`state <= 2'b01;`
71			`ready <= 0;`
72			`load <= 1;`
73			`end`
74			`end`
75			`endcase`
76			`end`
77			`end`
78
79			`endmodule`

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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ser/] [xmtbuf.v] - Blame information for rev 333