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[/] [eco32/] [trunk/] [fpga/] [mc-sim/] [src/] [cpu/] [cpu.v] - Blame information for rev 314

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1 301 hellwig
//
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// cpu.v -- the ECO32 CPU
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//
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`timescale 1ns/10ps
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`default_nettype none
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module cpu(clk, rst,
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           bus_stb, bus_we, bus_addr,
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           bus_din, bus_dout, bus_ack,
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           bus_irq);
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    input clk;                          // system clock
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    input rst;                          // system reset
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    output bus_stb;                     // bus strobe
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    output bus_we;                      // bus write enable
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    output [31:2] bus_addr;             // bus address (word address)
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    input [31:0] bus_din;                // bus data input, for reads
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    output [31:0] bus_dout;              // bus data output, for writes
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    input bus_ack;                      // bus acknowledge
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    input [15:0] bus_irq;                // bus interrupt requests
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  wire cpu_stb;
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  wire cpu_we;
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  wire [1:0] cpu_size;
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  wire [31:0] cpu_addr;
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  wire [31:0] cpu_din;
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  wire [31:0] cpu_dout;
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  wire cpu_ack;
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  wire [15:0] cpu_irq;
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  cpu_bus cpu_bus_1(
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    .clk(clk),
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    .rst(rst),
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    .bus_stb(bus_stb),
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    .bus_we(bus_we),
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    .bus_addr(bus_addr[31:2]),
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    .bus_din(bus_din[31:0]),
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    .bus_dout(bus_dout[31:0]),
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    .bus_ack(bus_ack),
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    .bus_irq(bus_irq[15:0]),
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    .cpu_stb(cpu_stb),
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    .cpu_we(cpu_we),
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    .cpu_size(cpu_size[1:0]),
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    .cpu_addr(cpu_addr[31:0]),
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    .cpu_din(cpu_din[31:0]),
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    .cpu_dout(cpu_dout[31:0]),
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    .cpu_ack(cpu_ack),
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    .cpu_irq(cpu_irq[15:0])
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  );
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  cpu_core cpu_core_1(
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    .clk(clk),
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    .rst(rst),
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    .bus_stb(cpu_stb),
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    .bus_we(cpu_we),
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    .bus_size(cpu_size[1:0]),
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    .bus_addr(cpu_addr[31:0]),
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    .bus_din(cpu_din[31:0]),
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    .bus_dout(cpu_dout[31:0]),
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    .bus_ack(cpu_ack),
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    .bus_irq(cpu_irq[15:0])
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  );
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endmodule

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