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[/] [eco32/] [trunk/] [fpga/] [mc-sim/] [src/] [ser/] [ser.v] - Blame information for rev 314

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Line No. Rev Author Line
1 301 hellwig
//
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// ser.v -- serial line interface
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//
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`timescale 1ns/10ps
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`default_nettype none
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`define TICKS_PER_CHAR          32'h00000200    // output speed
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module ser(i,                           // instance number
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           clk, rst,
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           stb, we, addr,
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           data_in, data_out,
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           ack, irq_r, irq_t);
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    input i;
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    input clk;
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    input rst;
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    input stb;
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    input we;
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    input [3:2] addr;
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    input [7:0] data_in;
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    output reg [7:0] data_out;
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    output ack;
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    output irq_r;
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    output irq_t;
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  wire wr_rcv_ctrl;
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  wire rd_rcv_data;
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  wire wr_xmt_ctrl;
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  wire wr_xmt_data;
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  reg [39:0] ser_data[0:255];             // space for 256 input requests
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  reg [7:0] ser_data_index;              // next location to read
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  wire [39:0] next_full;         // 40 bits from ser_data
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  wire [31:0] next_time;         // 32 bits delta clock ticks
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  wire [7:0] next_code;                  // 8 bits character code
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  reg [31:0] rcv_count;                  // input tick counter
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  integer ser_out;                      // file handle for serial output
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  reg [31:0] xmt_count;                  // output tick counter
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  reg rcv_rdy;
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  reg rcv_ien;
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  reg [7:0] rcv_data;
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  reg xmt_rdy;
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  reg xmt_ien;
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  reg [7:0] xmt_data;
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  assign wr_rcv_ctrl = (stb == 1 && we == 1 && addr == 2'b00) ? 1 : 0;
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  assign rd_rcv_data = (stb == 1 && we == 0 && addr == 2'b01) ? 1 : 0;
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  assign wr_xmt_ctrl = (stb == 1 && we == 1 && addr == 2'b10) ? 1 : 0;
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  assign wr_xmt_data = (stb == 1 && we == 1 && addr == 2'b11) ? 1 : 0;
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  initial begin
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    if (i == 0) begin
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      $readmemh("ser0.dat", ser_data);
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    end else begin
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      $readmemh("ser1.dat", ser_data);
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    end
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  end
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  assign next_full[39:0] = ser_data[ser_data_index];
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  assign next_time[31:0] = next_full[39:8];
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  assign next_code[7:0] = next_full[7:0];
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  always @(posedge clk) begin
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    if (rst) begin
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      ser_data_index <= 0;
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      rcv_count <= 0;
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      rcv_rdy <= 0;
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      rcv_data <= 0;
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    end else begin
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      if (rcv_count == 0) begin
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        rcv_count <= next_time;
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      end else
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      if (rcv_count == 1) begin
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        ser_data_index <= ser_data_index + 1;
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        rcv_count <= rcv_count - 1;
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        rcv_rdy <= 1;
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        rcv_data <= next_code;
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      end else begin
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        if (rcv_count != 32'hFFFFFFFF) begin
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          rcv_count <= rcv_count - 1;
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        end
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      end
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    end
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  end
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  always @(posedge clk) begin
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    if (rd_rcv_data == 1 && rcv_count != 1) begin
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      rcv_rdy <= 0;
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    end
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  end
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  initial begin
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    if (i == 0) begin
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      ser_out = $fopen("ser0.out", "w");
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    end else begin
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      ser_out = $fopen("ser1.out", "w");
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    end
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  end
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  always @(posedge clk) begin
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    if (rst) begin
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      xmt_count <= 0;
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      xmt_rdy <= 1;
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      xmt_data <= 0;
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    end else begin
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      if (wr_xmt_data) begin
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        xmt_count <= `TICKS_PER_CHAR;
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        xmt_rdy <= 0;
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        xmt_data <= data_in;
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      end else begin
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        if (xmt_count == 1) begin
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          xmt_count <= xmt_count - 1;
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          xmt_rdy <= 1;
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          $fdisplay(ser_out, "char = 0x%h", xmt_data);
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        end else begin
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          if (xmt_count != 0) begin
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            xmt_count <= xmt_count - 1;
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          end
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        end
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      end
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    end
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  end
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  always @(posedge clk) begin
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    if (rst) begin
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      rcv_ien <= 0;
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      xmt_ien <= 0;
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    end else begin
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      if (wr_rcv_ctrl) begin
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        rcv_ien <= data_in[1];
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      end
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      if (wr_xmt_ctrl) begin
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        xmt_ien <= data_in[1];
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      end
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    end
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  end
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  always @(*) begin
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    case (addr[3:2])
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      2'b00:
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        // rcv ctrl
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        data_out = { 6'b000000, rcv_ien, rcv_rdy };
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      2'b01:
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        // rcv data
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        data_out = rcv_data;
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      2'b10:
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        // xmt ctrl
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        data_out = { 6'b000000, xmt_ien, xmt_rdy };
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      2'b11:
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        // xmt data (cannot be read)
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        data_out = 8'hxx;
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      default:
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        data_out = 8'hxx;
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    endcase
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  end
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  assign ack = stb;
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  assign irq_r = rcv_ien & rcv_rdy;
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  assign irq_t = xmt_ien & xmt_rdy;
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endmodule

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