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[/] [eco32/] [trunk/] [fpga/] [mc-vl/] [src/] [dsp/] [dsp.v] - Blame information for rev 320

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1 308 hellwig
//
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// dsp.v -- character display interface
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//
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`timescale 1ns/10ps
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`default_nettype none
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module dsp(clk, rst,
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           stb, we, addr,
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           data_in, data_out, ack);
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    input clk;
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    input rst;
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    input stb;
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    input we;
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    input [13:2] addr;
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    input [15:0] data_in;
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    output [15:0] data_out;
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    output ack;
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  integer dsp_out;              // file handle for display output
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  reg [15:0] mem[0:4095]; // 32 x 128 attr/char display memory
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  initial begin
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    dsp_out = $fopen("dsp.out", "w");
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  end
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  always @(posedge clk) begin
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    if (stb & we) begin
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      mem[addr[13:2]] <= data_in[15:0];
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      $fdisplay(dsp_out,
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                "row = %d, col = %d, attr = 0x%h, char = 0x%h",
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                addr[13:9], addr[8:2], data_in[15:8], data_in[7:0]);
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    end
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  end
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  assign data_out[15:0] = mem[addr[13:2]];
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  assign ack = stb;
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endmodule

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