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[/] [eco32/] [trunk/] [fpga/] [mc-vl/] [src/] [ram/] [ram.v] - Blame information for rev 320

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1 308 hellwig
//
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// ram.v -- simulate external RAM
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//          8M x 32 bit = 32 MB
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//
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`timescale 1ns/10ps
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`default_nettype none
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//
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// use this set of parameters for minimal access times
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//
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//`define RD_CYCLES     4'd2    // # cycles for read, min = 2
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//`define WR_CYCLES     4'd2    // # cycles for write, min = 2
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//
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// use this set of parameters for realistic access times
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//
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`define RD_CYCLES       4'd14   // # cycles for read, min = 2
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`define WR_CYCLES       4'd6    // # cycles for write, min = 2
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module ram(clk, rst,
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           stb, we, addr,
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           data_in, data_out, ack);
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    input clk;
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    input rst;
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    input stb;
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    input we;
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    input [24:2] addr;
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    input [31:0] data_in;
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    output reg [31:0] data_out;
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    output ack;
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  reg [31:0] mem[0:8388607];
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  reg [3:0] counter;
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  always @(posedge clk) begin
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    if (stb) begin
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      if (we) begin
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        // write cycle
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        mem[addr] <= data_in;
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      end else begin
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        // read cycle
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        data_out <= mem[addr];
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      end
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    end
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  end
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  always @(posedge clk) begin
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    if (rst) begin
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      counter[3:0] <= 4'h0;
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    end else begin
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      if (counter[3:0] == 4'h0) begin
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        if (stb & ~we) begin
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          // a read may need some clock cycles
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          counter[3:0] <= `RD_CYCLES - 1;
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        end
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        if (stb & we) begin
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          // a write may need some clock cycles
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          counter[3:0] <= `WR_CYCLES - 1;
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        end
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      end else begin
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        counter[3:0] <= counter[3:0] - 1;
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      end
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    end
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  end
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  assign ack = (counter[3:0] == 4'h1) ? 1 : 0;
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endmodule

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