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[/] [eco32/] [trunk/] [hwtests/] [dsptest/] [start.s] - Blame information for rev 120

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;
; start.s -- startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0400000     ; monitor stack is at top of memory
 
        .set    PSW,0                    ; reg # of PSW
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import serinit
        .import ser0in
        .import ser0out
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cin
        .export cout
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
        .export wrtRndTLB
        .export probeTLB
        .export wait
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       interrupt
 
userMiss:
        j       userMiss
 
;***************************************************************
 
        .code
        .align  4
 
cin:
        j       ser0in
 
cout:
        j       ser0out
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; force CPU into a defined state
        mvts    $0,PSW                   ; disable interrupts and user mode
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        add     $9,$0,$0
        add     $10,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_ENTRY_HI
        mvts    $9,TLB_INDEX
        tbwi
        add     $8,$8,0x1000            ; all entries must be different
        add     $9,$9,1
        bne     $9,$10,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     serinit                 ; init serial interface
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
        ; void wrtRndTLB(Word entryHi, Word entryLo)
wrtRndTLB:
        mvts    $4,TLB_ENTRY_HI
        mvts    $5,TLB_ENTRY_LO
        tbwr
        jr      $31
 
        ; Word probeTLB(Word entryHi)
probeTLB:
        mvts    $4,TLB_ENTRY_HI
        tbs
        mvfs    $2,TLB_INDEX
        jr      $31
 
        ; void wait(int n)
wait:
        j       wait2
wait1:
        add     $4,$4,$0
        sub     $4,$4,1
wait2:
        bne     $4,$0,wait1
        jr      $31

Line No.	Rev	Author	Line
1	14	hellwig	`;`
2			`; start.s -- startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6			`.set stacktop,0xC0400000 ; monitor stack is at top of memory`
7
8			`.set PSW,0 ; reg # of PSW`
9			`.set TLB_INDEX,1 ; reg # of TLB Index`
10			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
11			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
12			`.set TLB_ENTRIES,32 ; number of TLB entries`
13
14			`;***************************************************************`
15
16			`.import _ecode`
17			`.import _edata`
18			`.import _ebss`
19
20			`.import serinit`
21			`.import ser0in`
22			`.import ser0out`
23
24			`.import main`
25
26			`.export _bcode`
27			`.export _bdata`
28			`.export _bbss`
29
30			`.export cin`
31			`.export cout`
32
33			`.export getTLB_HI`
34			`.export getTLB_LO`
35			`.export setTLB`
36			`.export wrtRndTLB`
37			`.export probeTLB`
38			`.export wait`
39
40			`;***************************************************************`
41
42			`.code`
43			`_bcode:`
44
45			`.data`
46			`_bdata:`
47
48			`.bss`
49			`_bbss:`
50
51			`;***************************************************************`
52
53			`.code`
54			`.align 4`
55
56			`reset:`
57			`j start`
58
59			`interrupt:`
60			`j interrupt`
61
62			`userMiss:`
63			`j userMiss`
64
65			`;***************************************************************`
66
67			`.code`
68			`.align 4`
69
70			`cin:`
71			`j ser0in`
72
73			`cout:`
74			`j ser0out`
75
76			`;***************************************************************`
77
78			`.code`
79			`.align 4`
80
81			`start:`
82			`; force CPU into a defined state`
83			`mvts $0,PSW ; disable interrupts and user mode`
84
85			`; initialize TLB`
86			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
87			`add $8,$0,dmapaddr ; by impossible virtual page number`
88			`add $9,$0,$0`
89			`add $10,$0,TLB_ENTRIES`
90			`tlbloop:`
91			`mvts $8,TLB_ENTRY_HI`
92			`mvts $9,TLB_INDEX`
93			`tbwi`
94			`add $8,$8,0x1000 ; all entries must be different`
95			`add $9,$9,1`
96			`bne $9,$10,tlbloop`
97
98			`; copy data segment`
99			`add $10,$0,_bdata ; lowest dst addr to be written to`
100			`add $8,$0,_edata ; one above the top dst addr`
101			`sub $9,$8,$10 ; $9 = size of data segment`
102			`add $9,$9,_ecode ; data is waiting right after code`
103			`j cpytest`
104			`cpyloop:`
105			`ldw $11,$9,0 ; src addr in $9`
106			`stw $11,$8,0 ; dst addr in $8`
107			`cpytest:`
108			`sub $8,$8,4 ; downward`
109			`sub $9,$9,4`
110			`bgeu $8,$10,cpyloop`
111
112			`; clear bss segment`
113			`add $8,$0,_bbss ; start with first word of bss`
114			`add $9,$0,_ebss ; this is one above the top`
115			`j clrtest`
116			`clrloop:`
117			`stw $0,$8,0 ; dst addr in $8`
118			`add $8,$8,4 ; upward`
119			`clrtest:`
120			`bltu $8,$9,clrloop`
121
122			`; now do some useful work`
123			`add $29,$0,stacktop ; setup monitor stack`
124			`jal serinit ; init serial interface`
125			`jal main ; enter command loop`
126
127			`; main should never return`
128			`j start ; just to be sure...`
129
130			`;***************************************************************`
131
132			`; Word getTLB_HI(int index)`
133			`getTLB_HI:`
134			`mvts $4,TLB_INDEX`
135			`tbri`
136			`mvfs $2,TLB_ENTRY_HI`
137			`jr $31`
138
139			`; Word getTLB_LO(int index)`
140			`getTLB_LO:`
141			`mvts $4,TLB_INDEX`
142			`tbri`
143			`mvfs $2,TLB_ENTRY_LO`
144			`jr $31`
145
146			`; void setTLB(int index, Word entryHi, Word entryLo)`
147			`setTLB:`
148			`mvts $4,TLB_INDEX`
149			`mvts $5,TLB_ENTRY_HI`
150			`mvts $6,TLB_ENTRY_LO`
151			`tbwi`
152			`jr $31`
153
154			`; void wrtRndTLB(Word entryHi, Word entryLo)`
155			`wrtRndTLB:`
156			`mvts $4,TLB_ENTRY_HI`
157			`mvts $5,TLB_ENTRY_LO`
158			`tbwr`
159			`jr $31`
160
161			`; Word probeTLB(Word entryHi)`
162			`probeTLB:`
163			`mvts $4,TLB_ENTRY_HI`
164			`tbs`
165			`mvfs $2,TLB_INDEX`
166			`jr $31`
167
168			`; void wait(int n)`
169			`wait:`
170			`j wait2`
171			`wait1:`
172			`add $4,$4,$0`
173			`sub $4,$4,1`
174			`wait2:`
175			`bne $4,$0,wait1`
176			`jr $31`

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[/] [eco32/] [trunk/] [hwtests/] [dsptest/] [start.s] - Blame information for rev 120