OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [hwtests/] [kbdtest/] [main.c] - Blame information for rev 182

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 14 hellwig
/*
2
 * main.c -- the main program
3
 */
4
 
5
 
6
#include "common.h"
7
#include "lib.h"
8
#include "start.h"
9
 
10
 
11
int charAvail = 0;
12
char charRead;
13
 
14
 
15
/**************************************************************/
16
 
17
 
18
/*
19
 * Interrupt and exception messages which will be shown if
20
 * the corresponding interrupt or exception is not handled.
21
 */
22
char *exceptionCause[32] = {
23
  /* 00 */  "terminal 0 transmitter interrupt",
24
  /* 01 */  "terminal 0 receiver interrupt",
25
  /* 02 */  "terminal 1 transmitter interrupt",
26
  /* 03 */  "terminal 1 receiver interrupt",
27
  /* 04 */  "keyboard interrupt",
28
  /* 05 */  "unknown interrupt 5",
29
  /* 06 */  "unknown interrupt 6",
30
  /* 07 */  "unknown interrupt 7",
31
  /* 08 */  "disk interrupt",
32
  /* 09 */  "unknown interrupt 9",
33
  /* 10 */  "unknown interrupt 10",
34
  /* 11 */  "unknown interrupt 11",
35
  /* 12 */  "unknown interrupt 12",
36
  /* 13 */  "unknown interrupt 13",
37 79 hellwig
  /* 14 */  "timer 0 interrupt",
38
  /* 15 */  "timer 1 interrupt",
39 14 hellwig
  /* 16 */  "bus timeout exception",
40
  /* 17 */  "illegal instruction exception",
41
  /* 18 */  "privileged instruction exception",
42
  /* 19 */  "divide instruction exception",
43
  /* 20 */  "trap instruction exception",
44
  /* 21 */  "TLB miss exception",
45
  /* 22 */  "TLB write exception",
46
  /* 23 */  "TLB invalid exception",
47
  /* 24 */  "illegal address exception",
48
  /* 25 */  "privileged address exception",
49
  /* 26 */  "unknown exception 26",
50
  /* 27 */  "unknown exception 27",
51
  /* 28 */  "unknown exception 28",
52
  /* 29 */  "unknown exception 29",
53
  /* 30 */  "unknown exception 30",
54
  /* 31 */  "unknown exception 31"
55
};
56
 
57
 
58
/*
59
 * This is the default interrupt service routine.
60
 * It simply panics with a message that tells the cause.
61
 */
62
void defaultISR(int irq, InterruptContext *icp) {
63
  printf("**** %s ****\n", exceptionCause[irq]);
64
  while (1) ;
65
}
66
 
67
 
68
/*
69
 * Initialize all interrupts and exceptions to the default ISR.
70
 * Enable interrupts.
71
 */
72
void initInterrupts(void) {
73
  int i;
74
 
75
  for (i = 0; i < 32; i++) {
76
    setISR(i, defaultISR);
77
  }
78
  enable();
79
}
80
 
81
 
82
/**************************************************************/
83
 
84
 
85
void kbdISR(int irq, InterruptContext *icp) {
86
  unsigned int *p;
87
 
88
  p = (unsigned int *) 0xF0200000;
89
  charRead = *(p + 1);
90
  charAvail = 1;
91
}
92
 
93
 
94
void kbdEnable(void) {
95
  unsigned int *p;
96
 
97
  p = (unsigned int *) 0xF0200000;
98
  *p = 2;
99
}
100
 
101
 
102
int main(void) {
103
  unsigned char c;
104
  int n;
105
 
106
  printf("Keyboard Test:\n");
107
  printf("initializing interrupts...\n");
108
  initInterrupts();
109
  printf("setting kbd ISR...\n");
110
  setISR(4, kbdISR);
111
  printf("enabling kbd interrupt mask bit...\n");
112
  setMask(getMask() | (1 << 4));
113
  printf("enabling interrupts in kbd controller...\n");
114
  kbdEnable();
115
  n = 0;
116
  while (1) {
117
    while (charAvail == 0) ;
118
    disable();
119
    c = charRead;
120
    charAvail = 0;
121
    enable();
122
    printf("%02X ", c);
123
    if (++n == 24) {
124
      n = 0;
125
      printf("\n");
126
    }
127
  }
128
  return 0;
129
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.