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[/] [eco32/] [trunk/] [hwtests/] [kbdtest/] [start.s] - Blame information for rev 71

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;
; start.s -- startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0400000     ; monitor stack is at top of memory
 
        .set    ICNTXT_SIZE,34 * 4      ; size of interrupt context
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
        .set    UM_SHIFT,26             ; curr user mode ctrl bit
        .set    UM,1 << UM_SHIFT
        .set    PUM_SHIFT,25            ; prev user mode ctrl bit
        .set    PUM,1 << PUM_SHIFT
        .set    OUM_SHIFT,24            ; old user mode ctrl bit
        .set    OUM,1 << OUM_SHIFT
        .set    IE_SHIFT,23             ; curr int enable ctrl bit
        .set    IE,1 << IE_SHIFT
        .set    PIE_SHIFT,22            ; prev int enable ctrl bit
        .set    PIE,1 << PIE_SHIFT
        .set    OIE_SHIFT,21            ; old int enable ctrl bit
        .set    OIE,1 << OIE_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import serinit
        .import ser0in
        .import ser0out
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cin
        .export cout
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
        .export wrtRndTLB
        .export probeTLB
        .export wait
 
        .export enable
        .export disable
        .export getMask
        .export setMask
        .export getISR
        .export setISR
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       userMiss
 
;***************************************************************
 
        .code
        .align  4
 
cin:
        j       ser0in
 
cout:
        j       ser0out
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; force CPU into a defined state
        mvts    $0,PSW                   ; disable interrupts and user mode
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        add     $9,$0,$0
        add     $10,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_ENTRY_HI
        mvts    $9,TLB_INDEX
        tbwi
        add     $8,$8,0x1000            ; all entries must be different
        add     $9,$9,1
        bne     $9,$10,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     serinit                 ; init serial interface
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
        ; void wrtRndTLB(Word entryHi, Word entryLo)
wrtRndTLB:
        mvts    $4,TLB_ENTRY_HI
        mvts    $5,TLB_ENTRY_LO
        tbwr
        jr      $31
 
        ; Word probeTLB(Word entryHi)
probeTLB:
        mvts    $4,TLB_ENTRY_HI
        tbs
        mvfs    $2,TLB_INDEX
        jr      $31
 
        ; void wait(int n)
wait:
        j       wait2
wait1:
        add     $4,$4,$0
        sub     $4,$4,1
wait2:
        bne     $4,$0,wait1
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; void enable(void)
enable:
        mvfs    $8,PSW
        or      $8,$8,IE
        mvts    $8,PSW
        jr      $31
 
        ; void disable(void)
disable:
        mvfs    $8,PSW
        and     $8,$8,~IE
        mvts    $8,PSW
        jr      $31
 
        ; U32 getMask(void)
getMask:
        mvfs    $8,PSW
        and     $2,$8,0x0000FFFF        ; return lower 16 bits only
        jr      $31
 
        ; U32 setMask(U32 mask)
setMask:
        mvfs    $8,PSW
        and     $2,$8,0x0000FFFF        ; return lower 16 bits only
        and     $4,$4,0x0000FFFF        ; use lower 16 bits only
        and     $8,$8,0xFFFF0000
        or      $8,$8,$4
        mvts    $8,PSW
        jr      $31
 
        ; ISR getISR(int irq)
getISR:
        sll     $4,$4,2
        ldw     $2,$4,irqsrv
        jr      $31
 
        ; ISR setISR(int irq, ISR isr)
setISR:
        sll     $4,$4,2
        ldw     $2,$4,irqsrv
        stw     $5,$4,irqsrv
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; general interrupt service routine
        ; only register $28 is available for bootstrapping
isr:
        .nosyn
        add     $28,$29,$0
        sub     $28,$28,ICNTXT_SIZE     ; $28 points to interrupt context
        stw     $0,$28,0*4                ; save registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,TLB_ENTRY_HI         ; save TLB EntryHi
        stw     $8,$28,32*4
        mvfs    $8,PSW                  ; save PSW
        stw     $8,$28,33*4
        add     $29,$28,$0               ; $29 is required to hold sp
        .syn
        add     $5,$29,$0                ; $5 = pointer to interrupt context
        slr     $4,$8,16                ; $4 = IRQ number
        and     $4,$4,0x1F
        sll     $8,$4,2                 ; $8 = 4 * IRQ number
        ldw     $8,$8,irqsrv            ; get addr of service routine
        jalr    $8                      ; call service routine
        .nosyn
        mvts    $0,PSW                   ; ISR may have enabled interrupts
        add     $28,$29,$0               ; $28 points to interrupt context
        ldw     $8,$28,32*4             ; restore TLB EntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $0,$28,0*4                ; restore registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ldw     $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,33*4            ; restore PSW
        mvts    $28,PSW
        rfx                             ; done
        .syn
 
;***************************************************************
 
        .data
        .align  4
 
irqsrv:
        .word   0                        ; 00: terminal 0 transmitter interrupt
        .word   0                        ; 01: terminal 0 receiver interrupt
        .word   0                        ; 02: terminal 1 transmitter interrupt
        .word   0                        ; 03: terminal 1 receiver interrupt
        .word   0                        ; 04: keyboard interrupt
        .word   0                        ; 05: unused
        .word   0                        ; 06: unused
        .word   0                        ; 07: unused
        .word   0                        ; 08: disk interrupt
        .word   0                        ; 09: unused
        .word   0                        ; 10: unused
        .word   0                        ; 11: unused
        .word   0                        ; 12: unused
        .word   0                        ; 13: unused
        .word   0                        ; 14: timer interrupt
        .word   0                        ; 15: unused
        .word   0                        ; 16: bus timeout exception
        .word   0                        ; 17: illegal instruction exception
        .word   0                        ; 18: privileged instruction exception
        .word   0                        ; 19: divide instruction exception
        .word   0                        ; 20: trap instruction exception
        .word   0                        ; 21: TLB miss exception
        .word   0                        ; 22: TLB write exception
        .word   0                        ; 23: TLB invalid exception
        .word   0                        ; 24: illegal address exception
        .word   0                        ; 25: privileged address exception
        .word   0                        ; 26: unused
        .word   0                        ; 27: unused
        .word   0                        ; 28: unused
        .word   0                        ; 29: unused
        .word   0                        ; 30: unused
        .word   0                        ; 31: unused

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [hwtests/] [kbdtest/] [start.s] - Blame information for rev 71

Line No.	Rev	Author	Line
1	14	hellwig	`;`
2			`; start.s -- startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6			`.set stacktop,0xC0400000 ; monitor stack is at top of memory`
7
8			`.set ICNTXT_SIZE,34 * 4 ; size of interrupt context`
9
10			`.set PSW,0 ; reg # of PSW`
11			`.set V_SHIFT,27 ; interrupt vector ctrl bit`
12			`.set V,1 << V_SHIFT`
13			`.set UM_SHIFT,26 ; curr user mode ctrl bit`
14			`.set UM,1 << UM_SHIFT`
15			`.set PUM_SHIFT,25 ; prev user mode ctrl bit`
16			`.set PUM,1 << PUM_SHIFT`
17			`.set OUM_SHIFT,24 ; old user mode ctrl bit`
18			`.set OUM,1 << OUM_SHIFT`
19			`.set IE_SHIFT,23 ; curr int enable ctrl bit`
20			`.set IE,1 << IE_SHIFT`
21			`.set PIE_SHIFT,22 ; prev int enable ctrl bit`
22			`.set PIE,1 << PIE_SHIFT`
23			`.set OIE_SHIFT,21 ; old int enable ctrl bit`
24			`.set OIE,1 << OIE_SHIFT`
25
26			`.set TLB_INDEX,1 ; reg # of TLB Index`
27			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
28			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
29			`.set TLB_ENTRIES,32 ; number of TLB entries`
30
31			`;***************************************************************`
32
33			`.import _ecode`
34			`.import _edata`
35			`.import _ebss`
36
37			`.import serinit`
38			`.import ser0in`
39			`.import ser0out`
40
41			`.import main`
42
43			`.export _bcode`
44			`.export _bdata`
45			`.export _bbss`
46
47			`.export cin`
48			`.export cout`
49
50			`.export getTLB_HI`
51			`.export getTLB_LO`
52			`.export setTLB`
53			`.export wrtRndTLB`
54			`.export probeTLB`
55			`.export wait`
56
57			`.export enable`
58			`.export disable`
59			`.export getMask`
60			`.export setMask`
61			`.export getISR`
62			`.export setISR`
63
64			`;***************************************************************`
65
66			`.code`
67			`_bcode:`
68
69			`.data`
70			`_bdata:`
71
72			`.bss`
73			`_bbss:`
74
75			`;***************************************************************`
76
77			`.code`
78			`.align 4`
79
80			`reset:`
81			`j start`
82
83			`interrupt:`
84			`j isr`
85
86			`userMiss:`
87			`j userMiss`
88
89			`;***************************************************************`
90
91			`.code`
92			`.align 4`
93
94			`cin:`
95			`j ser0in`
96
97			`cout:`
98			`j ser0out`
99
100			`;***************************************************************`
101
102			`.code`
103			`.align 4`
104
105			`start:`
106			`; force CPU into a defined state`
107			`mvts $0,PSW ; disable interrupts and user mode`
108
109			`; initialize TLB`
110			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
111			`add $8,$0,dmapaddr ; by impossible virtual page number`
112			`add $9,$0,$0`
113			`add $10,$0,TLB_ENTRIES`
114			`tlbloop:`
115			`mvts $8,TLB_ENTRY_HI`
116			`mvts $9,TLB_INDEX`
117			`tbwi`
118			`add $8,$8,0x1000 ; all entries must be different`
119			`add $9,$9,1`
120			`bne $9,$10,tlbloop`
121
122			`; copy data segment`
123			`add $10,$0,_bdata ; lowest dst addr to be written to`
124			`add $8,$0,_edata ; one above the top dst addr`
125			`sub $9,$8,$10 ; $9 = size of data segment`
126			`add $9,$9,_ecode ; data is waiting right after code`
127			`j cpytest`
128			`cpyloop:`
129			`ldw $11,$9,0 ; src addr in $9`
130			`stw $11,$8,0 ; dst addr in $8`
131			`cpytest:`
132			`sub $8,$8,4 ; downward`
133			`sub $9,$9,4`
134			`bgeu $8,$10,cpyloop`
135
136			`; clear bss segment`
137			`add $8,$0,_bbss ; start with first word of bss`
138			`add $9,$0,_ebss ; this is one above the top`
139			`j clrtest`
140			`clrloop:`
141			`stw $0,$8,0 ; dst addr in $8`
142			`add $8,$8,4 ; upward`
143			`clrtest:`
144			`bltu $8,$9,clrloop`
145
146			`; now do some useful work`
147			`add $29,$0,stacktop ; setup monitor stack`
148			`jal serinit ; init serial interface`
149			`jal main ; enter command loop`
150
151			`; main should never return`
152			`j start ; just to be sure...`
153
154			`;***************************************************************`
155
156			`; Word getTLB_HI(int index)`
157			`getTLB_HI:`
158			`mvts $4,TLB_INDEX`
159			`tbri`
160			`mvfs $2,TLB_ENTRY_HI`
161			`jr $31`
162
163			`; Word getTLB_LO(int index)`
164			`getTLB_LO:`
165			`mvts $4,TLB_INDEX`
166			`tbri`
167			`mvfs $2,TLB_ENTRY_LO`
168			`jr $31`
169
170			`; void setTLB(int index, Word entryHi, Word entryLo)`
171			`setTLB:`
172			`mvts $4,TLB_INDEX`
173			`mvts $5,TLB_ENTRY_HI`
174			`mvts $6,TLB_ENTRY_LO`
175			`tbwi`
176			`jr $31`
177
178			`; void wrtRndTLB(Word entryHi, Word entryLo)`
179			`wrtRndTLB:`
180			`mvts $4,TLB_ENTRY_HI`
181			`mvts $5,TLB_ENTRY_LO`
182			`tbwr`
183			`jr $31`
184
185			`; Word probeTLB(Word entryHi)`
186			`probeTLB:`
187			`mvts $4,TLB_ENTRY_HI`
188			`tbs`
189			`mvfs $2,TLB_INDEX`
190			`jr $31`
191
192			`; void wait(int n)`
193			`wait:`
194			`j wait2`
195			`wait1:`
196			`add $4,$4,$0`
197			`sub $4,$4,1`
198			`wait2:`
199			`bne $4,$0,wait1`
200			`jr $31`
201
202			`;***************************************************************`
203
204			`.code`
205			`.align 4`
206
207			`; void enable(void)`
208			`enable:`
209			`mvfs $8,PSW`
210			`or $8,$8,IE`
211			`mvts $8,PSW`
212			`jr $31`
213
214			`; void disable(void)`
215			`disable:`
216			`mvfs $8,PSW`
217			`and $8,$8,~IE`
218			`mvts $8,PSW`
219			`jr $31`
220
221			`; U32 getMask(void)`
222			`getMask:`
223			`mvfs $8,PSW`
224			`and $2,$8,0x0000FFFF ; return lower 16 bits only`
225			`jr $31`
226
227			`; U32 setMask(U32 mask)`
228			`setMask:`
229			`mvfs $8,PSW`
230			`and $2,$8,0x0000FFFF ; return lower 16 bits only`
231			`and $4,$4,0x0000FFFF ; use lower 16 bits only`
232			`and $8,$8,0xFFFF0000`
233			`or $8,$8,$4`
234			`mvts $8,PSW`
235			`jr $31`
236
237			`; ISR getISR(int irq)`
238			`getISR:`
239			`sll $4,$4,2`
240			`ldw $2,$4,irqsrv`
241			`jr $31`
242
243			`; ISR setISR(int irq, ISR isr)`
244			`setISR:`
245			`sll $4,$4,2`
246			`ldw $2,$4,irqsrv`
247			`stw $5,$4,irqsrv`
248			`jr $31`
249
250			`;***************************************************************`
251
252			`.code`
253			`.align 4`
254
255			`; general interrupt service routine`
256			`; only register $28 is available for bootstrapping`
257			`isr:`
258			`.nosyn`
259			`add $28,$29,$0`
260			`sub $28,$28,ICNTXT_SIZE ; $28 points to interrupt context`
261			`stw $0,$28,0*4 ; save registers`
262			`stw $1,$28,1*4`
263			`stw $2,$28,2*4`
264			`stw $3,$28,3*4`
265			`stw $4,$28,4*4`
266			`stw $5,$28,5*4`
267			`stw $6,$28,6*4`
268			`stw $7,$28,7*4`
269			`stw $8,$28,8*4`
270			`stw $9,$28,9*4`
271			`stw $10,$28,10*4`
272			`stw $11,$28,11*4`
273			`stw $12,$28,12*4`
274			`stw $13,$28,13*4`
275			`stw $14,$28,14*4`
276			`stw $15,$28,15*4`
277			`stw $16,$28,16*4`
278			`stw $17,$28,17*4`
279			`stw $18,$28,18*4`
280			`stw $19,$28,19*4`
281			`stw $20,$28,20*4`
282			`stw $21,$28,21*4`
283			`stw $22,$28,22*4`
284			`stw $23,$28,23*4`
285			`stw $24,$28,24*4`
286			`stw $25,$28,25*4`
287			`stw $26,$28,26*4`
288			`stw $27,$28,27*4`
289			`stw $28,$28,28*4`
290			`stw $29,$28,29*4`
291			`stw $30,$28,30*4`
292			`stw $31,$28,31*4`
293			`mvfs $8,TLB_ENTRY_HI ; save TLB EntryHi`
294			`stw $8,$28,32*4`
295			`mvfs $8,PSW ; save PSW`
296			`stw $8,$28,33*4`
297			`add $29,$28,$0 ; $29 is required to hold sp`
298			`.syn`
299			`add $5,$29,$0 ; $5 = pointer to interrupt context`
300			`slr $4,$8,16 ; $4 = IRQ number`
301			`and $4,$4,0x1F`
302			`sll $8,$4,2 ; $8 = 4 * IRQ number`
303			`ldw $8,$8,irqsrv ; get addr of service routine`
304			`jalr $8 ; call service routine`
305			`.nosyn`
306			`mvts $0,PSW ; ISR may have enabled interrupts`
307			`add $28,$29,$0 ; $28 points to interrupt context`
308			`ldw $8,$28,32*4 ; restore TLB EntryHi`
309			`mvts $8,TLB_ENTRY_HI`
310			`ldw $0,$28,0*4 ; restore registers`
311			`ldw $1,$28,1*4`
312			`ldw $2,$28,2*4`
313			`ldw $3,$28,3*4`
314			`ldw $4,$28,4*4`
315			`ldw $5,$28,5*4`
316			`ldw $6,$28,6*4`
317			`ldw $7,$28,7*4`
318			`ldw $8,$28,8*4`
319			`ldw $9,$28,9*4`
320			`ldw $10,$28,10*4`
321			`ldw $11,$28,11*4`
322			`ldw $12,$28,12*4`
323			`ldw $13,$28,13*4`
324			`ldw $14,$28,14*4`
325			`ldw $15,$28,15*4`
326			`ldw $16,$28,16*4`
327			`ldw $17,$28,17*4`
328			`ldw $18,$28,18*4`
329			`ldw $19,$28,19*4`
330			`ldw $20,$28,20*4`
331			`ldw $21,$28,21*4`
332			`ldw $22,$28,22*4`
333			`ldw $23,$28,23*4`
334			`ldw $24,$28,24*4`
335			`ldw $25,$28,25*4`
336			`ldw $26,$28,26*4`
337			`ldw $27,$28,27*4`
338			`ldw $28,$28,28*4`
339			`ldw $29,$28,29*4`
340			`ldw $30,$28,30*4`
341			`ldw $31,$28,31*4`
342			`ldw $28,$28,33*4 ; restore PSW`
343			`mvts $28,PSW`
344			`rfx ; done`
345			`.syn`
346
347			`;***************************************************************`
348
349			`.data`
350			`.align 4`
351
352			`irqsrv:`
353			`.word 0 ; 00: terminal 0 transmitter interrupt`
354			`.word 0 ; 01: terminal 0 receiver interrupt`
355			`.word 0 ; 02: terminal 1 transmitter interrupt`
356			`.word 0 ; 03: terminal 1 receiver interrupt`
357			`.word 0 ; 04: keyboard interrupt`
358			`.word 0 ; 05: unused`
359			`.word 0 ; 06: unused`
360			`.word 0 ; 07: unused`
361			`.word 0 ; 08: disk interrupt`
362			`.word 0 ; 09: unused`
363			`.word 0 ; 10: unused`
364			`.word 0 ; 11: unused`
365			`.word 0 ; 12: unused`
366			`.word 0 ; 13: unused`
367			`.word 0 ; 14: timer interrupt`
368			`.word 0 ; 15: unused`
369			`.word 0 ; 16: bus timeout exception`
370			`.word 0 ; 17: illegal instruction exception`
371			`.word 0 ; 18: privileged instruction exception`
372			`.word 0 ; 19: divide instruction exception`
373			`.word 0 ; 20: trap instruction exception`
374			`.word 0 ; 21: TLB miss exception`
375			`.word 0 ; 22: TLB write exception`
376			`.word 0 ; 23: TLB invalid exception`
377			`.word 0 ; 24: illegal address exception`
378			`.word 0 ; 25: privileged address exception`
379			`.word 0 ; 26: unused`
380			`.word 0 ; 27: unused`
381			`.word 0 ; 28: unused`
382			`.word 0 ; 29: unused`
383			`.word 0 ; 30: unused`
384			`.word 0 ; 31: unused`