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[/] [eco32/] [trunk/] [hwtests/] [xcptest/] [main.c] - Blame information for rev 14

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Line No. Rev Author Line
1 14 hellwig 
/*
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 * main.c -- the main program
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 */
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#include "common.h"
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#include "lib.h"
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#include "start.h"
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10 
 
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Word userMissTaken;
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static InterruptContext initial = {
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  /* regs */
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  0x00000011, 0x11111112, 0x22222213, 0x33333314,
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  0x44444415, 0x55555516, 0x66666617, 0x77777718,
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  0x88888819, 0x9999991A, 0xAAAAAA1B, 0xBBBBBB1C,
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  0xCCCCCC1D, 0xDDDDDD1E, 0xEEEEEE1F, 0xFFFFFF10,
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  0x00000021, 0x11111122, 0x22222223, 0x33333324,
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  0x44444425, 0x55555526, 0x66666627, 0x77777728,
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  0x88888829, 0x9999992A, 0xAAAAAA2B, 0xBBBBBB2C,
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  0xCCCCCC2D, 0xDDDDDD2E, 0xEEEEEE2F, 0xFFFFFF20,
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  /* PSW */
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  0x03FF5678,
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  /* TLB index */
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  0x87654321,
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  /* TLB EntryHi */
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  0x9ABCDEF0,
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  /* TLB EntryLo */
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  0x0FEDCBA9
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};
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static InterruptContext ic;
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static char *errorMessage[] = {
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  /*  0 */  "no error",
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  /*  1 */  "general register clobbered",
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  /*  2 */  "write to register 0 succeeded",
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  /*  3 */  "locus of exception incorrect",
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  /*  4 */  "TLB register clobbered",
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  /*  5 */  "vector bit incorrect",
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  /*  6 */  "user mode bits incorrect",
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  /*  7 */  "interrupt enable bits incorrect",
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  /*  8 */  "wrong exception number",
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  /*  9 */  "interrupt mask bits clobbered",
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  /* 10 */  "ISR entry was 'user miss'",
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  /* 11 */  "ISR entry was not 'user miss'",
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};
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static void flushTLB(void) {
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  Word invalPage;
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  int i;
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  invalPage = 0xC0000000;
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  for (i = 0; i < 32; i++) {
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    setTLB(i, invalPage, 0);
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    invalPage += (1 << 12);
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  }
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}
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static void check(unsigned int *res1, unsigned int *res2,
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                  Word expectedEntryHi) {
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  int i;
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  *res1 = 0;
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  *res2 = 0;
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  for (i = 0; i < 32; i++) {
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    if (ic.reg[i] != initial.reg[i]) {
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      *res1 |= (1 << i);
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    }
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  }
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  if ((ic.psw & 0x0FFFFFFF) != (initial.psw & 0x0FFFFFFF)) {
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    *res2 |= (1 << 0);
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  }
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  if ((ic.tlbIndex & 0x0000001F) != (initial.tlbIndex & 0x0000001F)) {
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    *res2 |= (1 << 1);
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  }
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  if ((ic.tlbHi & 0xFFFFF000) != (expectedEntryHi & 0xFFFFF000)) {
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    *res2 |= (1 << 2);
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  }
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  if ((ic.tlbLo & 0x3FFFF003) != (initial.tlbLo & 0x3FFFF003)) {
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    *res2 |= (1 << 3);
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  }
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}
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static int execTest(void (*run)(InterruptContext *icp),
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                    Word *expectedLocus,
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                    int expectedException,
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                    Bool execInUserMode,
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                    Bool clobberEntryHi,
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                    Bool shouldTakeUserMiss) {
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  unsigned int res1, res2;
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  int result;
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  Word *locus;
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  if (execInUserMode) {
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    initial.psw |= 1 << 26;
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  }
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  ic = initial;
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  flushTLB();
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  userMissTaken = 0xFFFFFFFF;
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  (*run)(&ic);
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  if (execInUserMode) {
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    locus = (Word *) (0xC0000000 | ic.reg[30]);
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  } else {
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    locus = (Word *) ic.reg[30];
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  }
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  if (!clobberEntryHi) {
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    check(&res1, &res2, initial.tlbHi);
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  } else {
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    if (shouldTakeUserMiss) {
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      check(&res1, &res2, initial.reg[3]);
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    } else {
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      check(&res1, &res2, initial.reg[11]);
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    }
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  }
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  result = 0;
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  if (((ic.psw >> 16) & 0x1F) != expectedException) {
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    result = 8;
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  } else
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  if (!shouldTakeUserMiss && userMissTaken != 0) {
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    result = 10;
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  } else
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  if (shouldTakeUserMiss && userMissTaken != (Word) &userMissTaken) {
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    result = 11;
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  } else
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  if (res1 != 0x50000001) {
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    result = 1;
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  } else
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  if (ic.reg[0] != 0x00000000) {
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    result = 2;
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  } else
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  if (locus != expectedLocus) {
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    result = 3;
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  } else
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  if (res2 != 0x00000001) {
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    result = 4;
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  } else
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  if (((ic.psw >> 27) & 0x01) != ((initial.psw >> 27) & 0x01)) {
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    result = 5;
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  } else
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  if (((ic.psw >> 24) & 0x07) != ((initial.psw >> 25) & 0x03)) {
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    result = 6;
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  } else
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  if (((ic.psw >> 21) & 0x07) != ((initial.psw >> 22) & 0x03)) {
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    result = 7;
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  } else
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  if (((ic.psw >>  0) & 0xFF) != ((initial.psw >>  0) & 0xFF)) {
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    result = 9;
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  }
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  if (execInUserMode) {
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    initial.psw &= ~(1 << 26);
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  }
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  return result;
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}
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163 
static struct {
164 
  char *name;
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  void (*run)(InterruptContext *icp);
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  Word *locus;
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  int exception;
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  Bool execInUserMode;
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  Bool clobberEntryHi;
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  Bool shouldTakeUserMiss;
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} tests[] = {
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  { "Trap instr test:\t\t\t",
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    xtest1,  &xtest1x,  20, false, false, false },
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  { "Illegal instr test:\t\t\t",
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    xtest2,  &xtest2x,  17, false, false, false },
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  { "Divide instr test 1 (div):\t\t",
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    xtest3,  &xtest3x,  19, false, false, false },
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  { "Divide instr test 2 (divi):\t\t",
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    xtest4,  &xtest4x,  19, false, false, false },
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  { "Divide instr test 3 (divu):\t\t",
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    xtest5,  &xtest5x,  19, false, false, false },
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  { "Divide instr test 4 (divui):\t\t",
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    xtest6,  &xtest6x,  19, false, false, false },
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  { "Divide instr test 5 (rem):\t\t",
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    xtest7,  &xtest7x,  19, false, false, false },
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  { "Divide instr test 6 (remi):\t\t",
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    xtest8,  &xtest8x,  19, false, false, false },
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  { "Divide instr test 7 (remu):\t\t",
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    xtest9,  &xtest9x,  19, false, false, false },
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  { "Divide instr test 8 (remui):\t\t",
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    xtest10, &xtest10x, 19, false, false, false },
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  { "Bus timeout test 1 (fetch):\t\t",
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    xtest11, &xtest11x, 16, false, false, false },
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  { "Bus timeout test 2 (load):\t\t",
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    xtest12, &xtest12x, 16, false, false, false },
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  { "Bus timeout test 3 (store):\t\t",
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    xtest13, &xtest13x, 16, false, false, false },
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  { "Privileged instr test 1 (rfx):\t\t",
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    xtest14, &xtest14x, 18, true,  false, false },
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  { "Privileged instr test 2 (mvts):\t\t",
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    xtest15, &xtest15x, 18, true,  false, false },
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  { "Privileged instr test 3 (tb..):\t\t",
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    xtest16, &xtest16x, 18, true,  false, false },
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  { "Privileged address test 1 (fetch):\t",
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    xtest17, &xtest17x, 25, true,  false, false },
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  { "Privileged address test 2 (load):\t",
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    xtest18, &xtest18x, 25, true,  false, false },
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  { "Privileged address test 3 (store):\t",
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    xtest19, &xtest19x, 25, true,  false, false },
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  { "Illegal address test 1 (fetch):\t\t",
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    xtest20, &xtest20x, 24, false, false, false },
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  { "Illegal address test 2 (fetch):\t\t",
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    xtest21, &xtest21x, 24, false, false, false },
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  { "Illegal address test 3 (ldw):\t\t",
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    xtest22, &xtest22x, 24, false, false, false },
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  { "Illegal address test 4 (ldw):\t\t",
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    xtest23, &xtest23x, 24, false, false, false },
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  { "Illegal address test 5 (ldh):\t\t",
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    xtest24, &xtest24x, 24, false, false, false },
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  { "Illegal address test 6 (stw):\t\t",
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    xtest25, &xtest25x, 24, false, false, false },
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  { "Illegal address test 7 (stw):\t\t",
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    xtest26, &xtest26x, 24, false, false, false },
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  { "Illegal address test 8 (sth):\t\t",
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    xtest27, &xtest27x, 24, false, false, false },
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  { "TLB user miss test 1 (fetch):\t\t",
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    xtest28, &xtest28x, 21, false, true,  true  },
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  { "TLB user miss test 2 (load):\t\t",
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    xtest29, &xtest29x, 21, false, true,  true  },
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  { "TLB user miss test 3 (store):\t\t",
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    xtest30, &xtest30x, 21, false, true,  true  },
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  { "TLB kernel miss test 1 (fetch):\t\t",
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    xtest31, &xtest31x, 21, false, true,  false },
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  { "TLB kernel miss test 2 (load):\t\t",
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    xtest32, &xtest32x, 21, false, true,  false },
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  { "TLB kernel miss test 3 (store):\t\t",
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    xtest33, &xtest33x, 21, false, true,  false },
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  { "TLB invalid test 1 (fetch):\t\t",
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    xtest34, &xtest34x, 23, false, true,  false },
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  { "TLB invalid test 2 (load):\t\t",
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    xtest35, &xtest35x, 23, false, true,  false },
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  { "TLB invalid test 3 (store):\t\t",
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    xtest36, &xtest36x, 23, false, true,  false },
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  { "TLB wrtprot test (store):\t\t",
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    xtest37, &xtest37x, 22, false, true,  false },
246 
};
247 
 
248 
 
249 
int main(void) {
250 
  int i;
251 
  int result;
252 
 
253 
  printf("\nStart of exception tests.\n\n");
254 
  for (i = 0; i < sizeof(tests)/sizeof(tests[0]); i++) {
255 
    printf("%s", tests[i].name);
256 
    result = execTest(tests[i].run,
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                      tests[i].locus,
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                      tests[i].exception,
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                      tests[i].execInUserMode,
260 
                      tests[i].clobberEntryHi,
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                      tests[i].shouldTakeUserMiss);
262 
    if (result == 0) {
263 
      printf("ok");
264 
    } else {
265 
      printf("failed (%s)", errorMessage[result]);
266 
    }
267 
    printf("\n");
268 
  }
269 
  printf("\nEnd of exception tests.\n");
270 
  while (1) ;
271 
  return 0;
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}

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