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[/] [eco32/] [trunk/] [hwtests/] [xcptest/] [main.c] - Blame information for rev 256

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Line No. Rev Author Line
1 14 hellwig 
/*
2 
 * main.c -- the main program
3 
 */
4 
 
5 
 
6 
#include "common.h"
7 
#include "lib.h"
8 
#include "start.h"
9 
 
10 
 
11 
Word userMissTaken;
12 
 
13 
 
14 
static InterruptContext initial = {
15 
  /* regs */
16 
  0x00000011, 0x11111112, 0x22222213, 0x33333314,
17 
  0x44444415, 0x55555516, 0x66666617, 0x77777718,
18 
  0x88888819, 0x9999991A, 0xAAAAAA1B, 0xBBBBBB1C,
19 
  0xCCCCCC1D, 0xDDDDDD1E, 0xEEEEEE1F, 0xFFFFFF10,
20 
  0x00000021, 0x11111122, 0x22222223, 0x33333324,
21 
  0x44444425, 0x55555526, 0x66666627, 0x77777728,
22 
  0x88888829, 0x9999992A, 0xAAAAAA2B, 0xBBBBBB2C,
23 
  0xCCCCCC2D, 0xDDDDDD2E, 0xEEEEEE2F, 0xFFFFFF20,
24 
  /* PSW */
25 
  0x03FF5678,
26 
  /* TLB index */
27 
  0x87654321,
28 
  /* TLB EntryHi */
29 
  0x9ABCDEF0,
30 
  /* TLB EntryLo */
31 80 hellwig 
  0x0FEDCBA9,
32 
  /* bad address */
33 
  0xDEADBEEF,
34 14 hellwig 
};
35 
 
36 
static InterruptContext ic;
37 
 
38 
 
39 
static char *errorMessage[] = {
40 
  /*  0 */  "no error",
41 
  /*  1 */  "general register clobbered",
42 
  /*  2 */  "write to register 0 succeeded",
43 
  /*  3 */  "locus of exception incorrect",
44 
  /*  4 */  "TLB register clobbered",
45 
  /*  5 */  "vector bit incorrect",
46 
  /*  6 */  "user mode bits incorrect",
47 
  /*  7 */  "interrupt enable bits incorrect",
48 
  /*  8 */  "wrong exception number",
49 
  /*  9 */  "interrupt mask bits clobbered",
50 
  /* 10 */  "ISR entry was 'user miss'",
51 
  /* 11 */  "ISR entry was not 'user miss'",
52 80 hellwig 
  /* 12 */  "bad address register clobbered",
53 
  /* 13 */  "bad address register incorrect",
54 14 hellwig 
};
55 
 
56 
 
57 
static void flushTLB(void) {
58 
  Word invalPage;
59 
  int i;
60 
 
61 
  invalPage = 0xC0000000;
62 
  for (i = 0; i < 32; i++) {
63 
    setTLB(i, invalPage, 0);
64 
    invalPage += (1 << 12);
65 
  }
66 
}
67 
 
68 
 
69 
static void check(unsigned int *res1, unsigned int *res2,
70 
                  Word expectedEntryHi) {
71 
  int i;
72 
 
73 
  *res1 = 0;
74 
  *res2 = 0;
75 
  for (i = 0; i < 32; i++) {
76 
    if (ic.reg[i] != initial.reg[i]) {
77 
      *res1 |= (1 << i);
78 
    }
79 
  }
80 
  if ((ic.psw & 0x0FFFFFFF) != (initial.psw & 0x0FFFFFFF)) {
81 
    *res2 |= (1 << 0);
82 
  }
83 
  if ((ic.tlbIndex & 0x0000001F) != (initial.tlbIndex & 0x0000001F)) {
84 
    *res2 |= (1 << 1);
85 
  }
86 
  if ((ic.tlbHi & 0xFFFFF000) != (expectedEntryHi & 0xFFFFF000)) {
87 
    *res2 |= (1 << 2);
88 
  }
89 
  if ((ic.tlbLo & 0x3FFFF003) != (initial.tlbLo & 0x3FFFF003)) {
90 
    *res2 |= (1 << 3);
91 
  }
92 
}
93 
 
94 
 
95 
static int execTest(void (*run)(InterruptContext *icp),
96 
                    Word *expectedLocus,
97 
                    int expectedException,
98 
                    Bool execInUserMode,
99 
                    Bool clobberEntryHi,
100 80 hellwig 
                    Bool shouldTakeUserMiss,
101 
                    Bool shouldSetBadAddr,
102 
                    Word expectedBadAddr) {
103 14 hellwig 
  unsigned int res1, res2;
104 
  int result;
105 
  Word *locus;
106 80 hellwig 
  Word badAddr;
107 14 hellwig 
 
108 
  if (execInUserMode) {
109 
    initial.psw |= 1 << 26;
110 
  }
111 
  ic = initial;
112 
  flushTLB();
113 
  userMissTaken = 0xFFFFFFFF;
114 
  (*run)(&ic);
115 
  if (execInUserMode) {
116 
    locus = (Word *) (0xC0000000 | ic.reg[30]);
117 
  } else {
118 
    locus = (Word *) ic.reg[30];
119 
  }
120 80 hellwig 
  badAddr = ic.badAddr;
121 14 hellwig 
  if (!clobberEntryHi) {
122 
    check(&res1, &res2, initial.tlbHi);
123 
  } else {
124 
    if (shouldTakeUserMiss) {
125 
      check(&res1, &res2, initial.reg[3]);
126 
    } else {
127 
      check(&res1, &res2, initial.reg[11]);
128 
    }
129 
  }
130 
  result = 0;
131 
  if (((ic.psw >> 16) & 0x1F) != expectedException) {
132 
    result = 8;
133 
  } else
134 
  if (!shouldTakeUserMiss && userMissTaken != 0) {
135 
    result = 10;
136 
  } else
137 
  if (shouldTakeUserMiss && userMissTaken != (Word) &userMissTaken) {
138 
    result = 11;
139 
  } else
140 
  if (res1 != 0x50000001) {
141 
    result = 1;
142 
  } else
143 
  if (ic.reg[0] != 0x00000000) {
144 
    result = 2;
145 
  } else
146 
  if (locus != expectedLocus) {
147 
    result = 3;
148 
  } else
149 80 hellwig 
  if (!shouldSetBadAddr && badAddr != initial.badAddr) {
150 
    result = 12;
151 
  } else
152 
  if (shouldSetBadAddr && badAddr != expectedBadAddr) {
153 
    result = 13;
154 
  } else
155 14 hellwig 
  if (res2 != 0x00000001) {
156 
    result = 4;
157 
  } else
158 
  if (((ic.psw >> 27) & 0x01) != ((initial.psw >> 27) & 0x01)) {
159 
    result = 5;
160 
  } else
161 
  if (((ic.psw >> 24) & 0x07) != ((initial.psw >> 25) & 0x03)) {
162 
    result = 6;
163 
  } else
164 
  if (((ic.psw >> 21) & 0x07) != ((initial.psw >> 22) & 0x03)) {
165 
    result = 7;
166 
  } else
167 
  if (((ic.psw >>  0) & 0xFF) != ((initial.psw >>  0) & 0xFF)) {
168 
    result = 9;
169 
  }
170 
  if (execInUserMode) {
171 256 hellwig 
    initial.psw &= ~((unsigned) 1 << 26);
172 14 hellwig 
  }
173 
  return result;
174 
}
175 
 
176 
 
177 
static struct {
178 
  char *name;
179 
  void (*run)(InterruptContext *icp);
180 
  Word *locus;
181 
  int exception;
182 
  Bool execInUserMode;
183 
  Bool clobberEntryHi;
184 
  Bool shouldTakeUserMiss;
185 80 hellwig 
  Bool shouldSetBadAddr;
186 
  Word expectedBadAddr;
187 14 hellwig 
} tests[] = {
188 
  { "Trap instr test:\t\t\t",
189 80 hellwig 
    xtest1,  &xtest1x,  20, false, false, false, false, 0 },
190 14 hellwig 
  { "Illegal instr test:\t\t\t",
191 80 hellwig 
    xtest2,  &xtest2x,  17, false, false, false, false, 0 },
192 14 hellwig 
  { "Divide instr test 1 (div):\t\t",
193 80 hellwig 
    xtest3,  &xtest3x,  19, false, false, false, false, 0 },
194 14 hellwig 
  { "Divide instr test 2 (divi):\t\t",
195 80 hellwig 
    xtest4,  &xtest4x,  19, false, false, false, false, 0 },
196 14 hellwig 
  { "Divide instr test 3 (divu):\t\t",
197 80 hellwig 
    xtest5,  &xtest5x,  19, false, false, false, false, 0 },
198 14 hellwig 
  { "Divide instr test 4 (divui):\t\t",
199 80 hellwig 
    xtest6,  &xtest6x,  19, false, false, false, false, 0 },
200 14 hellwig 
  { "Divide instr test 5 (rem):\t\t",
201 80 hellwig 
    xtest7,  &xtest7x,  19, false, false, false, false, 0 },
202 14 hellwig 
  { "Divide instr test 6 (remi):\t\t",
203 80 hellwig 
    xtest8,  &xtest8x,  19, false, false, false, false, 0 },
204 14 hellwig 
  { "Divide instr test 7 (remu):\t\t",
205 80 hellwig 
    xtest9,  &xtest9x,  19, false, false, false, false, 0 },
206 14 hellwig 
  { "Divide instr test 8 (remui):\t\t",
207 80 hellwig 
    xtest10, &xtest10x, 19, false, false, false, false, 0 },
208 14 hellwig 
  { "Bus timeout test 1 (fetch):\t\t",
209 80 hellwig 
    xtest11, &xtest11x, 16, false, false, false, false, 0 },
210 14 hellwig 
  { "Bus timeout test 2 (load):\t\t",
211 80 hellwig 
    xtest12, &xtest12x, 16, false, false, false, false, 0 },
212 14 hellwig 
  { "Bus timeout test 3 (store):\t\t",
213 80 hellwig 
    xtest13, &xtest13x, 16, false, false, false, false, 0 },
214 14 hellwig 
  { "Privileged instr test 1 (rfx):\t\t",
215 80 hellwig 
    xtest14, &xtest14x, 18, true,  false, false, false, 0 },
216 14 hellwig 
  { "Privileged instr test 2 (mvts):\t\t",
217 80 hellwig 
    xtest15, &xtest15x, 18, true,  false, false, false, 0 },
218 14 hellwig 
  { "Privileged instr test 3 (tb..):\t\t",
219 80 hellwig 
    xtest16, &xtest16x, 18, true,  false, false, false, 0 },
220 14 hellwig 
  { "Privileged address test 1 (fetch):\t",
221 80 hellwig 
    xtest17, &xtest17x, 25, true,  false, false, true,  0xffffff10 },
222 14 hellwig 
  { "Privileged address test 2 (load):\t",
223 80 hellwig 
    xtest18, &xtest18x, 25, true,  false, false, true,  0xffffff10 },
224 14 hellwig 
  { "Privileged address test 3 (store):\t",
225 80 hellwig 
    xtest19, &xtest19x, 25, true,  false, false, true,  0xffffff10 },
226 14 hellwig 
  { "Illegal address test 1 (fetch):\t\t",
227 80 hellwig 
    xtest20, &xtest20x, 24, false, false, false, true,  0x11111122 },
228 14 hellwig 
  { "Illegal address test 2 (fetch):\t\t",
229 80 hellwig 
    xtest21, &xtest21x, 24, false, false, false, true,  0x00000021 },
230 14 hellwig 
  { "Illegal address test 3 (ldw):\t\t",
231 80 hellwig 
    xtest22, &xtest22x, 24, false, false, false, true,  0xffffff12 },
232 14 hellwig 
  { "Illegal address test 4 (ldw):\t\t",
233 80 hellwig 
    xtest23, &xtest23x, 24, false, false, false, true,  0xffffff11 },
234 14 hellwig 
  { "Illegal address test 5 (ldh):\t\t",
235 80 hellwig 
    xtest24, &xtest24x, 24, false, false, false, true,  0xffffff11 },
236 14 hellwig 
  { "Illegal address test 6 (stw):\t\t",
237 80 hellwig 
    xtest25, &xtest25x, 24, false, false, false, true,  0xffffff12 },
238 14 hellwig 
  { "Illegal address test 7 (stw):\t\t",
239 80 hellwig 
    xtest26, &xtest26x, 24, false, false, false, true,  0xffffff11 },
240 14 hellwig 
  { "Illegal address test 8 (sth):\t\t",
241 80 hellwig 
    xtest27, &xtest27x, 24, false, false, false, true,  0xffffff11 },
242 14 hellwig 
  { "TLB user miss test 1 (fetch):\t\t",
243 80 hellwig 
    xtest28, &xtest28x, 21, false, true,  true,  true,  0x33333314 },
244 14 hellwig 
  { "TLB user miss test 2 (load):\t\t",
245 80 hellwig 
    xtest29, &xtest29x, 21, false, true,  true,  true,  0x33333314 },
246 14 hellwig 
  { "TLB user miss test 3 (store):\t\t",
247 80 hellwig 
    xtest30, &xtest30x, 21, false, true,  true,  true,  0x33333314 },
248 14 hellwig 
  { "TLB kernel miss test 1 (fetch):\t\t",
249 80 hellwig 
    xtest31, &xtest31x, 21, false, true,  false, true,  0xbbbbbb1c },
250 14 hellwig 
  { "TLB kernel miss test 2 (load):\t\t",
251 80 hellwig 
    xtest32, &xtest32x, 21, false, true,  false, true,  0xbbbbbb1c },
252 14 hellwig 
  { "TLB kernel miss test 3 (store):\t\t",
253 80 hellwig 
    xtest33, &xtest33x, 21, false, true,  false, true,  0xbbbbbb1c },
254 14 hellwig 
  { "TLB invalid test 1 (fetch):\t\t",
255 80 hellwig 
    xtest34, &xtest34x, 23, false, true,  false, true,  0xbbbbbb1c },
256 14 hellwig 
  { "TLB invalid test 2 (load):\t\t",
257 80 hellwig 
    xtest35, &xtest35x, 23, false, true,  false, true,  0xbbbbbb1c },
258 14 hellwig 
  { "TLB invalid test 3 (store):\t\t",
259 80 hellwig 
    xtest36, &xtest36x, 23, false, true,  false, true,  0xbbbbbb1c },
260 14 hellwig 
  { "TLB wrtprot test (store):\t\t",
261 80 hellwig 
    xtest37, &xtest37x, 22, false, true,  false, true,  0xbbbbbb1c },
262 14 hellwig 
};
263 
 
264 
 
265 
int main(void) {
266 
  int i;
267 
  int result;
268 
 
269 
  printf("\nStart of exception tests.\n\n");
270 
  for (i = 0; i < sizeof(tests)/sizeof(tests[0]); i++) {
271 
    printf("%s", tests[i].name);
272 
    result = execTest(tests[i].run,
273 
                      tests[i].locus,
274 
                      tests[i].exception,
275 
                      tests[i].execInUserMode,
276 
                      tests[i].clobberEntryHi,
277 80 hellwig 
                      tests[i].shouldTakeUserMiss,
278 
                      tests[i].shouldSetBadAddr,
279 
                      tests[i].expectedBadAddr);
280 14 hellwig 
    if (result == 0) {
281 
      printf("ok");
282 
    } else {
283 
      printf("failed (%s)", errorMessage[result]);
284 
    }
285 
    printf("\n");
286 
  }
287 
  printf("\nEnd of exception tests.\n");
288 
  while (1) ;
289 
  return 0;
290 
}

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