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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] [start.s] - Blame information for rev 141

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Line No. Rev Author Line
1 16 hellwig
;
2
; start.s -- ECO32 ROM monitor startup and support routines
3
;
4
 
5
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
6 50 hellwig
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
7 16 hellwig
 
8
        .set    PSW,0                    ; reg # of PSW
9 50 hellwig
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
10
        .set    V,1 << V_SHIFT
11
 
12 16 hellwig
        .set    TLB_INDEX,1             ; reg # of TLB Index
13
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
14
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
15
        .set    TLB_ENTRIES,32          ; number of TLB entries
16 84 hellwig
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
17 16 hellwig
 
18 84 hellwig
        .set    USER_CONTEXT_SIZE,37*4  ; size of user context
19 16 hellwig
 
20 50 hellwig
        .set    BIO_OUT,0xF1000000      ; board I/O output port
21
        .set    SPI_EN,0x80000000       ; SPI bus enable ctrl bit
22
 
23 16 hellwig
;***************************************************************
24
 
25
        .import _ecode
26
        .import _edata
27
        .import _ebss
28
 
29
        .import kbdinit
30
        .import kbdinchk
31
        .import kbdin
32
 
33
        .import dspinit
34
        .import dspoutchk
35
        .import dspout
36
 
37
        .import serinit
38
        .import ser0inchk
39
        .import ser0in
40
        .import ser0outchk
41
        .import ser0out
42
 
43
        .import sctcapctl
44
        .import sctioctl
45
        .import sctcapser
46
        .import sctioser
47
 
48
        .import main
49
 
50
        .export _bcode
51
        .export _bdata
52
        .export _bbss
53
 
54
        .export cinchk
55
        .export cin
56
        .export coutchk
57
        .export cout
58
        .export sinchk
59
        .export sin
60
        .export soutchk
61
        .export sout
62
        .export dskcap
63
        .export dskio
64
 
65 50 hellwig
        .export setISR
66
        .export setUMSR
67
        .export isrPtr
68
        .export umsrPtr
69
 
70 16 hellwig
        .export getTLB_HI
71
        .export getTLB_LO
72
        .export setTLB
73
 
74
        .export saveState
75
        .export monitorReturn
76
 
77
        .import userContext
78
        .export resume
79
 
80
;***************************************************************
81
 
82
        .code
83
_bcode:
84
 
85
        .data
86
_bdata:
87
 
88
        .bss
89
_bbss:
90
 
91
;***************************************************************
92
 
93
        .code
94
        .align  4
95
 
96
reset:
97
        j       start
98
 
99
interrupt:
100
        j       isr
101
 
102
userMiss:
103
        j       umsr
104
 
105
;***************************************************************
106
 
107
        .code
108
        .align  4
109
 
110
cinchk:
111
        j       kbdinchk
112
;       j       ser0inchk
113
 
114
cin:
115
        j       kbdin
116
;       j       ser0in
117
 
118
coutchk:
119
        j       dspoutchk
120
;       j       ser0outchk
121
 
122
cout:
123
        j       dspout
124
;       j       ser0out
125
 
126
sinchk:
127
        j       ser0inchk
128
 
129
sin:
130
        j       ser0in
131
 
132
soutchk:
133
        j       ser0outchk
134
 
135
sout:
136
        j       ser0out
137
 
138
dskcap:
139
        j       dcap
140
 
141
dskio:
142
        j       dio
143
 
144 50 hellwig
reserved1:
145
        j       reserved1
146
 
147
reserved2:
148
        j       reserved2
149
 
150
reserved3:
151
        j       reserved3
152
 
153
setISR:
154
        j       setISR1
155
 
156
setUMSR:
157
        j       setUMSR1
158
 
159 16 hellwig
;***************************************************************
160
 
161
        .code
162
        .align  4
163
 
164
start:
165 50 hellwig
        ; let irq/exc vectors point to RAM
166
        add     $8,$0,V
167
        mvts    $8,PSW
168 16 hellwig
 
169 50 hellwig
        ; disable flash ROM, enable SPI bus
170
        add     $8,$0,BIO_OUT
171
        add     $9,$0,SPI_EN
172
        stw     $9,$8,0
173
 
174 16 hellwig
        ; initialize TLB
175
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
176
        add     $8,$0,dmapaddr           ; by impossible virtual page number
177
        add     $9,$0,$0
178
        add     $10,$0,TLB_ENTRIES
179
tlbloop:
180
        mvts    $8,TLB_ENTRY_HI
181
        mvts    $9,TLB_INDEX
182
        tbwi
183
        add     $8,$8,0x1000            ; all entries must be different
184
        add     $9,$9,1
185
        bne     $9,$10,tlbloop
186
 
187
        ; copy data segment
188
        add     $10,$0,_bdata            ; lowest dst addr to be written to
189
        add     $8,$0,_edata             ; one above the top dst addr
190
        sub     $9,$8,$10               ; $9 = size of data segment
191
        add     $9,$9,_ecode            ; data is waiting right after code
192
        j       cpytest
193
cpyloop:
194
        ldw     $11,$9,0         ; src addr in $9
195
        stw     $11,$8,0         ; dst addr in $8
196
cpytest:
197
        sub     $8,$8,4                 ; downward
198
        sub     $9,$9,4
199
        bgeu    $8,$10,cpyloop
200
 
201
        ; clear bss segment
202
        add     $8,$0,_bbss              ; start with first word of bss
203
        add     $9,$0,_ebss              ; this is one above the top
204
        j       clrtest
205
clrloop:
206
        stw     $0,$8,0                   ; dst addr in $8
207
        add     $8,$8,4                 ; upward
208
clrtest:
209
        bltu    $8,$9,clrloop
210
 
211
        ; now do some useful work
212
        add     $29,$0,stacktop          ; setup monitor stack
213
        jal     dspinit                 ; init display
214
        jal     kbdinit                 ; init keyboard
215
        jal     serinit                 ; init serial interface
216
        jal     main                    ; enter command loop
217
 
218
        ; main should never return
219
        j       start                   ; just to be sure...
220
 
221
;***************************************************************
222
 
223 50 hellwig
        .code
224
        .align  4
225
 
226 16 hellwig
        ; Word getTLB_HI(int index)
227
getTLB_HI:
228
        mvts    $4,TLB_INDEX
229
        tbri
230
        mvfs    $2,TLB_ENTRY_HI
231
        jr      $31
232
 
233
        ; Word getTLB_LO(int index)
234
getTLB_LO:
235
        mvts    $4,TLB_INDEX
236
        tbri
237
        mvfs    $2,TLB_ENTRY_LO
238
        jr      $31
239
 
240
        ; void setTLB(int index, Word entryHi, Word entryLo)
241
setTLB:
242
        mvts    $4,TLB_INDEX
243
        mvts    $5,TLB_ENTRY_HI
244
        mvts    $6,TLB_ENTRY_LO
245
        tbwi
246
        jr      $31
247
 
248
;***************************************************************
249
 
250 50 hellwig
        .code
251
        .align  4
252
 
253 16 hellwig
        ; int dskcap(int dskno)
254
dcap:
255
        bne     $4,$0,dcapser
256
        j       sctcapctl
257
dcapser:
258
        j       sctcapser
259
 
260
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
261
dio:
262
        bne     $4,$0,dioser
263
        add     $4,$5,$0
264
        add     $5,$6,$0
265
        add     $6,$7,$0
266
        ldw     $7,$29,16
267
        j       sctioctl
268
dioser:
269
        add     $4,$5,$0
270
        add     $5,$6,$0
271
        add     $6,$7,$0
272
        ldw     $7,$29,16
273
        j       sctioser
274
 
275
;***************************************************************
276
 
277
        .code
278
        .align  4
279
 
280 50 hellwig
        ; void setISR(Word ptr)
281
setISR1:
282
        stw     $4,$0,isrPtr
283
        jr      $31
284
 
285
        ; void setUMSR(Word ptr)
286
setUMSR1:
287
        stw     $4,$0,umsrPtr
288
        jr      $31
289
 
290
        .data
291
        .align  4
292
 
293
isrPtr:
294
        .word   0
295
 
296
umsrPtr:
297
        .word   0
298
 
299
;***************************************************************
300
 
301
        .code
302
        .align  4
303
 
304 16 hellwig
        ; Bool saveState(MonitorState *msp)
305
        ; always return 'true' here
306
saveState:
307
        stw     $31,$4,0*4               ; return address
308
        stw     $29,$4,1*4              ; stack pointer
309
        stw     $16,$4,2*4              ; local variables
310
        stw     $17,$4,3*4
311
        stw     $18,$4,4*4
312
        stw     $19,$4,5*4
313
        stw     $20,$4,6*4
314
        stw     $21,$4,7*4
315
        stw     $22,$4,8*4
316
        stw     $23,$4,9*4
317
        add     $2,$0,1
318
        jr      $31
319
 
320
        ; load state when re-entering monitor
321
        ; this appears as if returning from saveState
322
        ; but the return value is 'false' here
323
loadState:
324
        ldw     $8,$0,monitorReturn
325
        beq     $8,$0,loadState          ; fatal error: monitor state lost
326
        ldw     $31,$8,0*4               ; return address
327
        ldw     $29,$8,1*4              ; stack pointer
328
        ldw     $16,$8,2*4              ; local variables
329
        ldw     $17,$8,3*4
330
        ldw     $18,$8,4*4
331
        ldw     $19,$8,5*4
332
        ldw     $20,$8,6*4
333
        ldw     $21,$8,7*4
334
        ldw     $22,$8,8*4
335
        ldw     $23,$8,9*4
336
        add     $2,$0,0
337
        jr      $31
338
 
339
        .bss
340
        .align  4
341
 
342
        ; extern MonitorState *monitorReturn
343
monitorReturn:
344
        .space  4
345
 
346
        ; extern UserContext userContext
347
userContext:
348
        .space  USER_CONTEXT_SIZE
349
 
350
;***************************************************************
351
 
352
        .code
353
        .align  4
354
 
355
        ; void resume(void)
356
        ; use userContext to load state
357
resume:
358
        mvts    $0,PSW
359
        add     $28,$0,userContext
360
        .nosyn
361
        ldw     $8,$28,33*4             ; tlbIndex
362
        mvts    $8,TLB_INDEX
363 50 hellwig
        ldw     $8,$28,34*4             ; tlbEntryHi
364 16 hellwig
        mvts    $8,TLB_ENTRY_HI
365
        ldw     $8,$28,35*4             ; tlbEntryLo
366
        mvts    $8,TLB_ENTRY_LO
367 84 hellwig
        ldw     $8,$28,36*4             ; badAddress
368
        mvts    $8,BAD_ADDRESS
369 16 hellwig
        ;ldw    $0,$28,0*4              ; registers
370
        ldw     $1,$28,1*4
371
        ldw     $2,$28,2*4
372
        ldw     $3,$28,3*4
373
        ldw     $4,$28,4*4
374
        ldw     $5,$28,5*4
375
        ldw     $6,$28,6*4
376
        ldw     $7,$28,7*4
377
        ldw     $8,$28,8*4
378
        ldw     $9,$28,9*4
379
        ldw     $10,$28,10*4
380
        ldw     $11,$28,11*4
381
        ldw     $12,$28,12*4
382
        ldw     $13,$28,13*4
383
        ldw     $14,$28,14*4
384
        ldw     $15,$28,15*4
385
        ldw     $16,$28,16*4
386
        ldw     $17,$28,17*4
387
        ldw     $18,$28,18*4
388
        ldw     $19,$28,19*4
389
        ldw     $20,$28,20*4
390
        ldw     $21,$28,21*4
391
        ldw     $22,$28,22*4
392
        ldw     $23,$28,23*4
393
        ldw     $24,$28,24*4
394
        ldw     $25,$28,25*4
395
        ldw     $26,$28,26*4
396
        ldw     $27,$28,27*4
397
        ;ldw    $28,$28,28*4
398
        ldw     $29,$28,29*4
399
        ldw     $30,$28,30*4
400
        ldw     $31,$28,31*4
401
        ldw     $28,$28,32*4            ; psw
402
        mvts    $28,PSW
403
        rfx
404
        .syn
405
 
406
        ; interrupt entry
407
        ; use userContext to store state
408
isr:
409
umsr:
410
        .nosyn
411
        ldhi    $28,userContext
412
        or      $28,$28,userContext
413
        stw     $0,$28,0*4                ; registers
414
        stw     $1,$28,1*4
415
        stw     $2,$28,2*4
416
        stw     $3,$28,3*4
417
        stw     $4,$28,4*4
418
        stw     $5,$28,5*4
419
        stw     $6,$28,6*4
420
        stw     $7,$28,7*4
421
        stw     $8,$28,8*4
422
        stw     $9,$28,9*4
423
        stw     $10,$28,10*4
424
        stw     $11,$28,11*4
425
        stw     $12,$28,12*4
426
        stw     $13,$28,13*4
427
        stw     $14,$28,14*4
428
        stw     $15,$28,15*4
429
        stw     $16,$28,16*4
430
        stw     $17,$28,17*4
431
        stw     $18,$28,18*4
432
        stw     $19,$28,19*4
433
        stw     $20,$28,20*4
434
        stw     $21,$28,21*4
435
        stw     $22,$28,22*4
436
        stw     $23,$28,23*4
437
        stw     $24,$28,24*4
438
        stw     $25,$28,25*4
439
        stw     $26,$28,26*4
440
        stw     $27,$28,27*4
441
        stw     $28,$28,28*4
442
        stw     $29,$28,29*4
443
        stw     $30,$28,30*4
444
        stw     $31,$28,31*4
445
        mvfs    $8,PSW
446
        stw     $8,$28,32*4             ; psw
447
        mvfs    $8,TLB_INDEX
448
        stw     $8,$28,33*4             ; tlbIndex
449
        mvfs    $8,TLB_ENTRY_HI
450
        stw     $8,$28,34*4             ; tlbEntryHi
451
        mvfs    $8,TLB_ENTRY_LO
452
        stw     $8,$28,35*4             ; tlbEntryLo
453 84 hellwig
        mvfs    $8,BAD_ADDRESS
454
        stw     $8,$28,36*4             ; badAddress
455 16 hellwig
        .syn
456
        j       loadState

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