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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] [start.s] - Blame information for rev 180

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
        .set    BIO_OUT,0xF1000000      ; board I/O output port
        .set    SPI_EN,0x80000000       ; SPI bus enable ctrl bit
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import serinit
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import sctcapctl
        .import sctioctl
        .import sctcapser
        .import sctioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export sinchk
        .export sin
        .export soutchk
        .export sout
        .export dskcap
        .export dskio
 
        .export setISR
        .export setUMSR
        .export isrPtr
        .export umsrPtr
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
cinchk:
        j       kbdinchk
;       j       ser0inchk
 
cin:
        j       kbdin
;       j       ser0in
 
coutchk:
        j       dspoutchk
;       j       ser0outchk
 
cout:
        j       dspout
;       j       ser0out
 
sinchk:
        j       ser0inchk
 
sin:
        j       ser0in
 
soutchk:
        j       ser0outchk
 
sout:
        j       ser0out
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved1:
        j       reserved1
 
reserved2:
        j       reserved2
 
reserved3:
        j       reserved3
 
setISR:
        j       setISR1
 
setUMSR:
        j       setUMSR1
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; disable flash ROM, enable SPI bus
        add     $8,$0,BIO_OUT
        add     $9,$0,SPI_EN
        stw     $9,$8,0
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        add     $9,$0,$0
        add     $10,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_ENTRY_HI
        mvts    $9,TLB_INDEX
        tbwi
        add     $8,$8,0x1000            ; all entries must be different
        add     $9,$9,1
        bne     $9,$10,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     dspinit                 ; init display
        jal     kbdinit                 ; init keyboard
        jal     serinit                 ; init serial interface
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       sctcapctl
dcapser:
        j       sctcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; void setISR(Word ptr)
setISR1:
        stw     $4,$0,isrPtr
        jr      $31
 
        ; void setUMSR(Word ptr)
setUMSR1:
        stw     $4,$0,umsrPtr
        jr      $31
 
        .data
        .align  4
 
isrPtr:
        .word   0
 
umsrPtr:
        .word   0
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$28,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$28,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$28,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$28,37*4             ; badAccess
        .syn
        j       loadState

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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] [start.s] - Blame information for rev 180

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6	50	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
7	16	hellwig
8			`.set PSW,0 ; reg # of PSW`
9	50	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
10			`.set V,1 << V_SHIFT`
11
12	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
13			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
14			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
15			`.set TLB_ENTRIES,32 ; number of TLB entries`
16	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
17	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
18	16	hellwig
19	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
20	16	hellwig
21	50	hellwig	`.set BIO_OUT,0xF1000000 ; board I/O output port`
22			`.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit`
23
24	16	hellwig	`;***************************************************************`
25
26			`.import _ecode`
27			`.import _edata`
28			`.import _ebss`
29
30			`.import kbdinit`
31			`.import kbdinchk`
32			`.import kbdin`
33
34			`.import dspinit`
35			`.import dspoutchk`
36			`.import dspout`
37
38			`.import serinit`
39			`.import ser0inchk`
40			`.import ser0in`
41			`.import ser0outchk`
42			`.import ser0out`
43
44			`.import sctcapctl`
45			`.import sctioctl`
46			`.import sctcapser`
47			`.import sctioser`
48
49			`.import main`
50
51			`.export _bcode`
52			`.export _bdata`
53			`.export _bbss`
54
55			`.export cinchk`
56			`.export cin`
57			`.export coutchk`
58			`.export cout`
59			`.export sinchk`
60			`.export sin`
61			`.export soutchk`
62			`.export sout`
63			`.export dskcap`
64			`.export dskio`
65
66	50	hellwig	`.export setISR`
67			`.export setUMSR`
68			`.export isrPtr`
69			`.export umsrPtr`
70
71	16	hellwig	`.export getTLB_HI`
72			`.export getTLB_LO`
73			`.export setTLB`
74
75			`.export saveState`
76			`.export monitorReturn`
77
78			`.import userContext`
79			`.export resume`
80
81			`;***************************************************************`
82
83			`.code`
84			`_bcode:`
85
86			`.data`
87			`_bdata:`
88
89			`.bss`
90			`_bbss:`
91
92			`;***************************************************************`
93
94			`.code`
95			`.align 4`
96
97			`reset:`
98			`j start`
99
100			`interrupt:`
101			`j isr`
102
103			`userMiss:`
104			`j umsr`
105
106			`;***************************************************************`
107
108			`.code`
109			`.align 4`
110
111			`cinchk:`
112			`j kbdinchk`
113			`; j ser0inchk`
114
115			`cin:`
116			`j kbdin`
117			`; j ser0in`
118
119			`coutchk:`
120			`j dspoutchk`
121			`; j ser0outchk`
122
123			`cout:`
124			`j dspout`
125			`; j ser0out`
126
127			`sinchk:`
128			`j ser0inchk`
129
130			`sin:`
131			`j ser0in`
132
133			`soutchk:`
134			`j ser0outchk`
135
136			`sout:`
137			`j ser0out`
138
139			`dskcap:`
140			`j dcap`
141
142			`dskio:`
143			`j dio`
144
145	50	hellwig	`reserved1:`
146			`j reserved1`
147
148			`reserved2:`
149			`j reserved2`
150
151			`reserved3:`
152			`j reserved3`
153
154			`setISR:`
155			`j setISR1`
156
157			`setUMSR:`
158			`j setUMSR1`
159
160	16	hellwig	`;***************************************************************`
161
162			`.code`
163			`.align 4`
164
165			`start:`
166	50	hellwig	`; let irq/exc vectors point to RAM`
167			`add $8,$0,V`
168			`mvts $8,PSW`
169	16	hellwig
170	50	hellwig	`; disable flash ROM, enable SPI bus`
171			`add $8,$0,BIO_OUT`
172			`add $9,$0,SPI_EN`
173			`stw $9,$8,0`
174
175	16	hellwig	`; initialize TLB`
176			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
177			`add $8,$0,dmapaddr ; by impossible virtual page number`
178			`add $9,$0,$0`
179			`add $10,$0,TLB_ENTRIES`
180			`tlbloop:`
181			`mvts $8,TLB_ENTRY_HI`
182			`mvts $9,TLB_INDEX`
183			`tbwi`
184			`add $8,$8,0x1000 ; all entries must be different`
185			`add $9,$9,1`
186			`bne $9,$10,tlbloop`
187
188			`; copy data segment`
189			`add $10,$0,_bdata ; lowest dst addr to be written to`
190			`add $8,$0,_edata ; one above the top dst addr`
191			`sub $9,$8,$10 ; $9 = size of data segment`
192			`add $9,$9,_ecode ; data is waiting right after code`
193			`j cpytest`
194			`cpyloop:`
195			`ldw $11,$9,0 ; src addr in $9`
196			`stw $11,$8,0 ; dst addr in $8`
197			`cpytest:`
198			`sub $8,$8,4 ; downward`
199			`sub $9,$9,4`
200			`bgeu $8,$10,cpyloop`
201
202			`; clear bss segment`
203			`add $8,$0,_bbss ; start with first word of bss`
204			`add $9,$0,_ebss ; this is one above the top`
205			`j clrtest`
206			`clrloop:`
207			`stw $0,$8,0 ; dst addr in $8`
208			`add $8,$8,4 ; upward`
209			`clrtest:`
210			`bltu $8,$9,clrloop`
211
212			`; now do some useful work`
213			`add $29,$0,stacktop ; setup monitor stack`
214			`jal dspinit ; init display`
215			`jal kbdinit ; init keyboard`
216			`jal serinit ; init serial interface`
217			`jal main ; enter command loop`
218
219			`; main should never return`
220			`j start ; just to be sure...`
221
222			`;***************************************************************`
223
224	50	hellwig	`.code`
225			`.align 4`
226
227	16	hellwig	`; Word getTLB_HI(int index)`
228			`getTLB_HI:`
229			`mvts $4,TLB_INDEX`
230			`tbri`
231			`mvfs $2,TLB_ENTRY_HI`
232			`jr $31`
233
234			`; Word getTLB_LO(int index)`
235			`getTLB_LO:`
236			`mvts $4,TLB_INDEX`
237			`tbri`
238			`mvfs $2,TLB_ENTRY_LO`
239			`jr $31`
240
241			`; void setTLB(int index, Word entryHi, Word entryLo)`
242			`setTLB:`
243			`mvts $4,TLB_INDEX`
244			`mvts $5,TLB_ENTRY_HI`
245			`mvts $6,TLB_ENTRY_LO`
246			`tbwi`
247			`jr $31`
248
249			`;***************************************************************`
250
251	50	hellwig	`.code`
252			`.align 4`
253
254	16	hellwig	`; int dskcap(int dskno)`
255			`dcap:`
256			`bne $4,$0,dcapser`
257			`j sctcapctl`
258			`dcapser:`
259			`j sctcapser`
260
261			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
262			`dio:`
263			`bne $4,$0,dioser`
264			`add $4,$5,$0`
265			`add $5,$6,$0`
266			`add $6,$7,$0`
267			`ldw $7,$29,16`
268			`j sctioctl`
269			`dioser:`
270			`add $4,$5,$0`
271			`add $5,$6,$0`
272			`add $6,$7,$0`
273			`ldw $7,$29,16`
274			`j sctioser`
275
276			`;***************************************************************`
277
278			`.code`
279			`.align 4`
280
281	50	hellwig	`; void setISR(Word ptr)`
282			`setISR1:`
283			`stw $4,$0,isrPtr`
284			`jr $31`
285
286			`; void setUMSR(Word ptr)`
287			`setUMSR1:`
288			`stw $4,$0,umsrPtr`
289			`jr $31`
290
291			`.data`
292			`.align 4`
293
294			`isrPtr:`
295			`.word 0`
296
297			`umsrPtr:`
298			`.word 0`
299
300			`;***************************************************************`
301
302			`.code`
303			`.align 4`
304
305	16	hellwig	`; Bool saveState(MonitorState *msp)`
306			`; always return 'true' here`
307			`saveState:`
308			`stw $31,$4,0*4 ; return address`
309			`stw $29,$4,1*4 ; stack pointer`
310			`stw $16,$4,2*4 ; local variables`
311			`stw $17,$4,3*4`
312			`stw $18,$4,4*4`
313			`stw $19,$4,5*4`
314			`stw $20,$4,6*4`
315			`stw $21,$4,7*4`
316			`stw $22,$4,8*4`
317			`stw $23,$4,9*4`
318			`add $2,$0,1`
319			`jr $31`
320
321			`; load state when re-entering monitor`
322			`; this appears as if returning from saveState`
323			`; but the return value is 'false' here`
324			`loadState:`
325			`ldw $8,$0,monitorReturn`
326			`beq $8,$0,loadState ; fatal error: monitor state lost`
327			`ldw $31,$8,0*4 ; return address`
328			`ldw $29,$8,1*4 ; stack pointer`
329			`ldw $16,$8,2*4 ; local variables`
330			`ldw $17,$8,3*4`
331			`ldw $18,$8,4*4`
332			`ldw $19,$8,5*4`
333			`ldw $20,$8,6*4`
334			`ldw $21,$8,7*4`
335			`ldw $22,$8,8*4`
336			`ldw $23,$8,9*4`
337			`add $2,$0,0`
338			`jr $31`
339
340			`.bss`
341			`.align 4`
342
343			`; extern MonitorState *monitorReturn`
344			`monitorReturn:`
345			`.space 4`
346
347			`; extern UserContext userContext`
348			`userContext:`
349			`.space USER_CONTEXT_SIZE`
350
351			`;***************************************************************`
352
353			`.code`
354			`.align 4`
355
356			`; void resume(void)`
357			`; use userContext to load state`
358			`resume:`
359			`mvts $0,PSW`
360			`add $28,$0,userContext`
361			`.nosyn`
362			`ldw $8,$28,33*4 ; tlbIndex`
363			`mvts $8,TLB_INDEX`
364	50	hellwig	`ldw $8,$28,34*4 ; tlbEntryHi`
365	16	hellwig	`mvts $8,TLB_ENTRY_HI`
366			`ldw $8,$28,35*4 ; tlbEntryLo`
367			`mvts $8,TLB_ENTRY_LO`
368	84	hellwig	`ldw $8,$28,36*4 ; badAddress`
369			`mvts $8,BAD_ADDRESS`
370	180	hellwig	`ldw $8,$28,37*4 ; badAccess`
371			`mvts $8,BAD_ACCESS`
372	16	hellwig	`;ldw $0,$28,0*4 ; registers`
373			`ldw $1,$28,1*4`
374			`ldw $2,$28,2*4`
375			`ldw $3,$28,3*4`
376			`ldw $4,$28,4*4`
377			`ldw $5,$28,5*4`
378			`ldw $6,$28,6*4`
379			`ldw $7,$28,7*4`
380			`ldw $8,$28,8*4`
381			`ldw $9,$28,9*4`
382			`ldw $10,$28,10*4`
383			`ldw $11,$28,11*4`
384			`ldw $12,$28,12*4`
385			`ldw $13,$28,13*4`
386			`ldw $14,$28,14*4`
387			`ldw $15,$28,15*4`
388			`ldw $16,$28,16*4`
389			`ldw $17,$28,17*4`
390			`ldw $18,$28,18*4`
391			`ldw $19,$28,19*4`
392			`ldw $20,$28,20*4`
393			`ldw $21,$28,21*4`
394			`ldw $22,$28,22*4`
395			`ldw $23,$28,23*4`
396			`ldw $24,$28,24*4`
397			`ldw $25,$28,25*4`
398			`ldw $26,$28,26*4`
399			`ldw $27,$28,27*4`
400			`;ldw $28,$28,28*4`
401			`ldw $29,$28,29*4`
402			`ldw $30,$28,30*4`
403			`ldw $31,$28,31*4`
404			`ldw $28,$28,32*4 ; psw`
405			`mvts $28,PSW`
406			`rfx`
407			`.syn`
408
409			`; interrupt entry`
410			`; use userContext to store state`
411			`isr:`
412			`umsr:`
413			`.nosyn`
414			`ldhi $28,userContext`
415			`or $28,$28,userContext`
416			`stw $0,$28,0*4 ; registers`
417			`stw $1,$28,1*4`
418			`stw $2,$28,2*4`
419			`stw $3,$28,3*4`
420			`stw $4,$28,4*4`
421			`stw $5,$28,5*4`
422			`stw $6,$28,6*4`
423			`stw $7,$28,7*4`
424			`stw $8,$28,8*4`
425			`stw $9,$28,9*4`
426			`stw $10,$28,10*4`
427			`stw $11,$28,11*4`
428			`stw $12,$28,12*4`
429			`stw $13,$28,13*4`
430			`stw $14,$28,14*4`
431			`stw $15,$28,15*4`
432			`stw $16,$28,16*4`
433			`stw $17,$28,17*4`
434			`stw $18,$28,18*4`
435			`stw $19,$28,19*4`
436			`stw $20,$28,20*4`
437			`stw $21,$28,21*4`
438			`stw $22,$28,22*4`
439			`stw $23,$28,23*4`
440			`stw $24,$28,24*4`
441			`stw $25,$28,25*4`
442			`stw $26,$28,26*4`
443			`stw $27,$28,27*4`
444			`stw $28,$28,28*4`
445			`stw $29,$28,29*4`
446			`stw $30,$28,30*4`
447			`stw $31,$28,31*4`
448			`mvfs $8,PSW`
449			`stw $8,$28,32*4 ; psw`
450			`mvfs $8,TLB_INDEX`
451			`stw $8,$28,33*4 ; tlbIndex`
452			`mvfs $8,TLB_ENTRY_HI`
453			`stw $8,$28,34*4 ; tlbEntryHi`
454			`mvfs $8,TLB_ENTRY_LO`
455			`stw $8,$28,35*4 ; tlbEntryLo`
456	84	hellwig	`mvfs $8,BAD_ADDRESS`
457			`stw $8,$28,36*4 ; badAddress`
458	180	hellwig	`mvfs $8,BAD_ACCESS`
459			`stw $8,$28,37*4 ; badAccess`
460	16	hellwig	`.syn`
461			`j loadState`