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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] [start.s] - Blame information for rev 182

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
        .set    BIO_OUT,0xF1000000      ; board I/O output port
        .set    SPI_EN,0x80000000       ; SPI bus enable ctrl bit
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import ser0init
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import ser1init
        .import ser1inchk
        .import ser1in
        .import ser1outchk
        .import ser1out
 
        .import dskinit
        .import dskcapctl
        .import dskioctl
        .import dskcapser
        .import dskioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export sinchk
        .export sin
        .export soutchk
        .export sout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
cinchk:
        j       kbdinchk
;       j       ser0inchk
 
cin:
        j       kbdin
;       j       ser0in
 
coutchk:
        j       dspoutchk
;       j       ser0outchk
 
cout:
        j       dspout
;       j       ser0out
 
sinchk:
        j       ser0inchk
 
sin:
        j       ser0in
 
soutchk:
        j       ser0outchk
 
sout:
        j       ser0out
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved1:
        j       reserved1
 
reserved2:
        j       reserved2
 
reserved3:
        j       reserved3
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; disable flash ROM, enable SPI bus
        add     $8,$0,BIO_OUT
        add     $9,$0,SPI_EN
        stw     $9,$8,0
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        mvts    $8,TLB_ENTRY_HI
        add     $8,$0,$0
        add     $9,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_INDEX
        tbwi
        add     $8,$8,1
        bne     $8,$9,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     dspinit                 ; init display
        jal     kbdinit                 ; init keyboard
        jal     ser0init                ; init serial line 0
        jal     ser1init                ; init serial line 1
        jal     dskinit                 ; init disk
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       dskcapctl
dcapser:
        j       dskcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$28,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$28,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$28,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$28,37*4             ; badAccess
        .syn
        j       loadState

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6	50	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
7	16	hellwig
8			`.set PSW,0 ; reg # of PSW`
9	50	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
10			`.set V,1 << V_SHIFT`
11
12	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
13			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
14			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
15			`.set TLB_ENTRIES,32 ; number of TLB entries`
16	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
17	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
18	16	hellwig
19	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
20	16	hellwig
21	50	hellwig	`.set BIO_OUT,0xF1000000 ; board I/O output port`
22			`.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit`
23
24	16	hellwig	`;***************************************************************`
25
26			`.import _ecode`
27			`.import _edata`
28			`.import _ebss`
29
30	182	hellwig	`.import dspinit`
31			`.import dspoutchk`
32			`.import dspout`
33
34	16	hellwig	`.import kbdinit`
35			`.import kbdinchk`
36			`.import kbdin`
37
38	182	hellwig	`.import ser0init`
39	16	hellwig	`.import ser0inchk`
40			`.import ser0in`
41			`.import ser0outchk`
42			`.import ser0out`
43
44	182	hellwig	`.import ser1init`
45			`.import ser1inchk`
46			`.import ser1in`
47			`.import ser1outchk`
48			`.import ser1out`
49	16	hellwig
50	182	hellwig	`.import dskinit`
51			`.import dskcapctl`
52			`.import dskioctl`
53			`.import dskcapser`
54			`.import dskioser`
55
56	16	hellwig	`.import main`
57
58			`.export _bcode`
59			`.export _bdata`
60			`.export _bbss`
61
62			`.export cinchk`
63			`.export cin`
64			`.export coutchk`
65			`.export cout`
66			`.export sinchk`
67			`.export sin`
68			`.export soutchk`
69			`.export sout`
70			`.export dskcap`
71			`.export dskio`
72
73			`.export getTLB_HI`
74			`.export getTLB_LO`
75			`.export setTLB`
76
77			`.export saveState`
78			`.export monitorReturn`
79
80			`.import userContext`
81			`.export resume`
82
83			`;***************************************************************`
84
85			`.code`
86			`_bcode:`
87
88			`.data`
89			`_bdata:`
90
91			`.bss`
92			`_bbss:`
93
94			`;***************************************************************`
95
96			`.code`
97			`.align 4`
98
99			`reset:`
100			`j start`
101
102			`interrupt:`
103			`j isr`
104
105			`userMiss:`
106			`j umsr`
107
108			`;***************************************************************`
109
110			`.code`
111			`.align 4`
112
113			`cinchk:`
114			`j kbdinchk`
115			`; j ser0inchk`
116
117			`cin:`
118			`j kbdin`
119			`; j ser0in`
120
121			`coutchk:`
122			`j dspoutchk`
123			`; j ser0outchk`
124
125			`cout:`
126			`j dspout`
127			`; j ser0out`
128
129			`sinchk:`
130			`j ser0inchk`
131
132			`sin:`
133			`j ser0in`
134
135			`soutchk:`
136			`j ser0outchk`
137
138			`sout:`
139			`j ser0out`
140
141			`dskcap:`
142			`j dcap`
143
144			`dskio:`
145			`j dio`
146
147	50	hellwig	`reserved1:`
148			`j reserved1`
149
150			`reserved2:`
151			`j reserved2`
152
153			`reserved3:`
154			`j reserved3`
155
156	16	hellwig	`;***************************************************************`
157
158			`.code`
159			`.align 4`
160
161			`start:`
162	50	hellwig	`; let irq/exc vectors point to RAM`
163			`add $8,$0,V`
164			`mvts $8,PSW`
165	16	hellwig
166	50	hellwig	`; disable flash ROM, enable SPI bus`
167			`add $8,$0,BIO_OUT`
168			`add $9,$0,SPI_EN`
169			`stw $9,$8,0`
170
171	16	hellwig	`; initialize TLB`
172			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
173			`add $8,$0,dmapaddr ; by impossible virtual page number`
174	182	hellwig	`mvts $8,TLB_ENTRY_HI`
175			`add $8,$0,$0`
176			`add $9,$0,TLB_ENTRIES`
177	16	hellwig	`tlbloop:`
178	182	hellwig	`mvts $8,TLB_INDEX`
179	16	hellwig	`tbwi`
180	182	hellwig	`add $8,$8,1`
181			`bne $8,$9,tlbloop`
182	16	hellwig
183			`; copy data segment`
184			`add $10,$0,_bdata ; lowest dst addr to be written to`
185			`add $8,$0,_edata ; one above the top dst addr`
186			`sub $9,$8,$10 ; $9 = size of data segment`
187			`add $9,$9,_ecode ; data is waiting right after code`
188			`j cpytest`
189			`cpyloop:`
190			`ldw $11,$9,0 ; src addr in $9`
191			`stw $11,$8,0 ; dst addr in $8`
192			`cpytest:`
193			`sub $8,$8,4 ; downward`
194			`sub $9,$9,4`
195			`bgeu $8,$10,cpyloop`
196
197			`; clear bss segment`
198			`add $8,$0,_bbss ; start with first word of bss`
199			`add $9,$0,_ebss ; this is one above the top`
200			`j clrtest`
201			`clrloop:`
202			`stw $0,$8,0 ; dst addr in $8`
203			`add $8,$8,4 ; upward`
204			`clrtest:`
205			`bltu $8,$9,clrloop`
206
207			`; now do some useful work`
208			`add $29,$0,stacktop ; setup monitor stack`
209			`jal dspinit ; init display`
210			`jal kbdinit ; init keyboard`
211	182	hellwig	`jal ser0init ; init serial line 0`
212			`jal ser1init ; init serial line 1`
213			`jal dskinit ; init disk`
214	16	hellwig	`jal main ; enter command loop`
215
216			`; main should never return`
217			`j start ; just to be sure...`
218
219			`;***************************************************************`
220
221	50	hellwig	`.code`
222			`.align 4`
223
224	16	hellwig	`; Word getTLB_HI(int index)`
225			`getTLB_HI:`
226			`mvts $4,TLB_INDEX`
227			`tbri`
228			`mvfs $2,TLB_ENTRY_HI`
229			`jr $31`
230
231			`; Word getTLB_LO(int index)`
232			`getTLB_LO:`
233			`mvts $4,TLB_INDEX`
234			`tbri`
235			`mvfs $2,TLB_ENTRY_LO`
236			`jr $31`
237
238			`; void setTLB(int index, Word entryHi, Word entryLo)`
239			`setTLB:`
240			`mvts $4,TLB_INDEX`
241			`mvts $5,TLB_ENTRY_HI`
242			`mvts $6,TLB_ENTRY_LO`
243			`tbwi`
244			`jr $31`
245
246			`;***************************************************************`
247
248	50	hellwig	`.code`
249			`.align 4`
250
251	16	hellwig	`; int dskcap(int dskno)`
252			`dcap:`
253			`bne $4,$0,dcapser`
254	182	hellwig	`j dskcapctl`
255	16	hellwig	`dcapser:`
256	182	hellwig	`j dskcapser`
257	16	hellwig
258			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
259			`dio:`
260			`bne $4,$0,dioser`
261			`add $4,$5,$0`
262			`add $5,$6,$0`
263			`add $6,$7,$0`
264			`ldw $7,$29,16`
265	182	hellwig	`j dskioctl`
266	16	hellwig	`dioser:`
267			`add $4,$5,$0`
268			`add $5,$6,$0`
269			`add $6,$7,$0`
270			`ldw $7,$29,16`
271	182	hellwig	`j dskioser`
272	16	hellwig
273			`;***************************************************************`
274
275			`.code`
276			`.align 4`
277
278			`; Bool saveState(MonitorState *msp)`
279			`; always return 'true' here`
280			`saveState:`
281			`stw $31,$4,0*4 ; return address`
282			`stw $29,$4,1*4 ; stack pointer`
283			`stw $16,$4,2*4 ; local variables`
284			`stw $17,$4,3*4`
285			`stw $18,$4,4*4`
286			`stw $19,$4,5*4`
287			`stw $20,$4,6*4`
288			`stw $21,$4,7*4`
289			`stw $22,$4,8*4`
290			`stw $23,$4,9*4`
291			`add $2,$0,1`
292			`jr $31`
293
294			`; load state when re-entering monitor`
295			`; this appears as if returning from saveState`
296			`; but the return value is 'false' here`
297			`loadState:`
298			`ldw $8,$0,monitorReturn`
299			`beq $8,$0,loadState ; fatal error: monitor state lost`
300			`ldw $31,$8,0*4 ; return address`
301			`ldw $29,$8,1*4 ; stack pointer`
302			`ldw $16,$8,2*4 ; local variables`
303			`ldw $17,$8,3*4`
304			`ldw $18,$8,4*4`
305			`ldw $19,$8,5*4`
306			`ldw $20,$8,6*4`
307			`ldw $21,$8,7*4`
308			`ldw $22,$8,8*4`
309			`ldw $23,$8,9*4`
310			`add $2,$0,0`
311			`jr $31`
312
313			`.bss`
314			`.align 4`
315
316			`; extern MonitorState *monitorReturn`
317			`monitorReturn:`
318			`.space 4`
319
320			`; extern UserContext userContext`
321			`userContext:`
322			`.space USER_CONTEXT_SIZE`
323
324			`;***************************************************************`
325
326			`.code`
327			`.align 4`
328
329			`; void resume(void)`
330			`; use userContext to load state`
331			`resume:`
332			`mvts $0,PSW`
333			`add $28,$0,userContext`
334			`.nosyn`
335			`ldw $8,$28,33*4 ; tlbIndex`
336			`mvts $8,TLB_INDEX`
337	50	hellwig	`ldw $8,$28,34*4 ; tlbEntryHi`
338	16	hellwig	`mvts $8,TLB_ENTRY_HI`
339			`ldw $8,$28,35*4 ; tlbEntryLo`
340			`mvts $8,TLB_ENTRY_LO`
341	84	hellwig	`ldw $8,$28,36*4 ; badAddress`
342			`mvts $8,BAD_ADDRESS`
343	180	hellwig	`ldw $8,$28,37*4 ; badAccess`
344			`mvts $8,BAD_ACCESS`
345	16	hellwig	`;ldw $0,$28,0*4 ; registers`
346			`ldw $1,$28,1*4`
347			`ldw $2,$28,2*4`
348			`ldw $3,$28,3*4`
349			`ldw $4,$28,4*4`
350			`ldw $5,$28,5*4`
351			`ldw $6,$28,6*4`
352			`ldw $7,$28,7*4`
353			`ldw $8,$28,8*4`
354			`ldw $9,$28,9*4`
355			`ldw $10,$28,10*4`
356			`ldw $11,$28,11*4`
357			`ldw $12,$28,12*4`
358			`ldw $13,$28,13*4`
359			`ldw $14,$28,14*4`
360			`ldw $15,$28,15*4`
361			`ldw $16,$28,16*4`
362			`ldw $17,$28,17*4`
363			`ldw $18,$28,18*4`
364			`ldw $19,$28,19*4`
365			`ldw $20,$28,20*4`
366			`ldw $21,$28,21*4`
367			`ldw $22,$28,22*4`
368			`ldw $23,$28,23*4`
369			`ldw $24,$28,24*4`
370			`ldw $25,$28,25*4`
371			`ldw $26,$28,26*4`
372			`ldw $27,$28,27*4`
373			`;ldw $28,$28,28*4`
374			`ldw $29,$28,29*4`
375			`ldw $30,$28,30*4`
376			`ldw $31,$28,31*4`
377			`ldw $28,$28,32*4 ; psw`
378			`mvts $28,PSW`
379			`rfx`
380			`.syn`
381
382			`; interrupt entry`
383			`; use userContext to store state`
384			`isr:`
385			`umsr:`
386			`.nosyn`
387			`ldhi $28,userContext`
388			`or $28,$28,userContext`
389			`stw $0,$28,0*4 ; registers`
390			`stw $1,$28,1*4`
391			`stw $2,$28,2*4`
392			`stw $3,$28,3*4`
393			`stw $4,$28,4*4`
394			`stw $5,$28,5*4`
395			`stw $6,$28,6*4`
396			`stw $7,$28,7*4`
397			`stw $8,$28,8*4`
398			`stw $9,$28,9*4`
399			`stw $10,$28,10*4`
400			`stw $11,$28,11*4`
401			`stw $12,$28,12*4`
402			`stw $13,$28,13*4`
403			`stw $14,$28,14*4`
404			`stw $15,$28,15*4`
405			`stw $16,$28,16*4`
406			`stw $17,$28,17*4`
407			`stw $18,$28,18*4`
408			`stw $19,$28,19*4`
409			`stw $20,$28,20*4`
410			`stw $21,$28,21*4`
411			`stw $22,$28,22*4`
412			`stw $23,$28,23*4`
413			`stw $24,$28,24*4`
414			`stw $25,$28,25*4`
415			`stw $26,$28,26*4`
416			`stw $27,$28,27*4`
417			`stw $28,$28,28*4`
418			`stw $29,$28,29*4`
419			`stw $30,$28,30*4`
420			`stw $31,$28,31*4`
421			`mvfs $8,PSW`
422			`stw $8,$28,32*4 ; psw`
423			`mvfs $8,TLB_INDEX`
424			`stw $8,$28,33*4 ; tlbIndex`
425			`mvfs $8,TLB_ENTRY_HI`
426			`stw $8,$28,34*4 ; tlbEntryHi`
427			`mvfs $8,TLB_ENTRY_LO`
428			`stw $8,$28,35*4 ; tlbEntryLo`
429	84	hellwig	`mvfs $8,BAD_ADDRESS`
430			`stw $8,$28,36*4 ; badAddress`
431	180	hellwig	`mvfs $8,BAD_ACCESS`
432			`stw $8,$28,37*4 ; badAccess`
433	16	hellwig	`.syn`
434			`j loadState`

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