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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] [start.s] - Blame information for rev 201

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    CIO_CTL,0x00            ; set console to keyboard/display
;       .set    CIO_CTL,0x03            ; set console to serial line 0
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
        .set    BIO_OUT,0xF1000000      ; board I/O output port
        .set    SPI_EN,0x80000000       ; SPI bus enable ctrl bit
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import ser0init
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import ser1init
        .import ser1inchk
        .import ser1in
        .import ser1outchk
        .import ser1out
 
        .import dskinitctl
        .import dskcapctl
        .import dskioctl
 
        .import dskinitser
        .import dskcapser
        .import dskioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export setcon
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
startup:
        j       start
 
interrupt:
        j       debug
 
userMiss:
        j       debug
 
monitor:
        j       debug
 
;***************************************************************
 
        .code
        .align  4
 
setcon:
        j       setcio
 
cinchk:
        j       cichk
 
cin:
        j       ci
 
coutchk:
        j       cochk
 
cout:
        j       co
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved_11:
        j       reserved_11
 
reserved_12:
        j       reserved_12
 
reserved_13:
        j       reserved_13
 
reserved_14:
        j       reserved_14
 
reserved_15:
        j       reserved_15
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; disable flash ROM, enable SPI bus
        add     $8,$0,BIO_OUT
        add     $9,$0,SPI_EN
        stw     $9,$8,0
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        mvts    $8,TLB_ENTRY_HI
        add     $8,$0,$0
        add     $9,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_INDEX
        tbwi
        add     $8,$8,1
        bne     $8,$9,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; initialize I/O
        add     $29,$0,stacktop          ; setup monitor stack
        jal     kbdinit                 ; init keyboard
        jal     dspinit                 ; init display
        jal     ser0init                ; init serial line 0
        jal     ser1init                ; init serial line 1
        jal     dskinitctl              ; init disk (controller)
        jal     dskinitser              ; init disk (serial line)
        add     $4,$0,CIO_CTL            ; set console
        jal     setcio
 
        ; call main
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .data
        .align  4
 
cioctl:
        .byte   0
 
        .code
        .align  4
 
        ; void setcon(Byte ctl)
setcio:
        stb     $4,$0,cioctl
        j       $31
 
        ; int cinchk(void)
cichk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,cichk1
        j       kbdinchk
cichk1:
        j       ser0inchk
 
        ; char cin(void)
ci:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,ci1
        j       kbdin
ci1:
        j       ser0in
 
        ; int coutchk(void)
cochk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,cochk1
        j       dspoutchk
cochk1:
        j       ser0outchk
 
        ; void cout(char c)
co:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,co1
        j       dspout
co1:
        j       ser0out
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       dskcapctl
dcapser:
        j       dskcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $24,$0,userContext
        .nosyn
        ldw     $8,$24,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$24,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$24,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$24,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$24,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$24,0*4              ; registers
        ldw     $1,$24,1*4
        ldw     $2,$24,2*4
        ldw     $3,$24,3*4
        ldw     $4,$24,4*4
        ldw     $5,$24,5*4
        ldw     $6,$24,6*4
        ldw     $7,$24,7*4
        ldw     $8,$24,8*4
        ldw     $9,$24,9*4
        ldw     $10,$24,10*4
        ldw     $11,$24,11*4
        ldw     $12,$24,12*4
        ldw     $13,$24,13*4
        ldw     $14,$24,14*4
        ldw     $15,$24,15*4
        ldw     $16,$24,16*4
        ldw     $17,$24,17*4
        ldw     $18,$24,18*4
        ldw     $19,$24,19*4
        ldw     $20,$24,20*4
        ldw     $21,$24,21*4
        ldw     $22,$24,22*4
        ldw     $23,$24,23*4
        ;ldw    $24,$24,24*4
        ldw     $25,$24,25*4
        ldw     $26,$24,26*4
        ldw     $27,$24,27*4
        ldw     $28,$24,28*4
        ldw     $29,$24,29*4
        ldw     $30,$24,30*4
        ldw     $31,$24,31*4
        ldw     $24,$24,32*4            ; psw
        mvts    $24,PSW
        rfx
        .syn
 
        ; debug entry
        ; use userContext to store state
debug:
        .nosyn
        ldhi    $24,userContext
        or      $24,$24,userContext
        stw     $0,$24,0*4                ; registers
        stw     $1,$24,1*4
        stw     $2,$24,2*4
        stw     $3,$24,3*4
        stw     $4,$24,4*4
        stw     $5,$24,5*4
        stw     $6,$24,6*4
        stw     $7,$24,7*4
        stw     $8,$24,8*4
        stw     $9,$24,9*4
        stw     $10,$24,10*4
        stw     $11,$24,11*4
        stw     $12,$24,12*4
        stw     $13,$24,13*4
        stw     $14,$24,14*4
        stw     $15,$24,15*4
        stw     $16,$24,16*4
        stw     $17,$24,17*4
        stw     $18,$24,18*4
        stw     $19,$24,19*4
        stw     $20,$24,20*4
        stw     $21,$24,21*4
        stw     $22,$24,22*4
        stw     $23,$24,23*4
        stw     $24,$24,24*4
        stw     $25,$24,25*4
        stw     $26,$24,26*4
        stw     $27,$24,27*4
        stw     $28,$24,28*4
        stw     $29,$24,29*4
        stw     $30,$24,30*4
        stw     $31,$24,31*4
        mvfs    $8,PSW
        stw     $8,$24,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$24,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$24,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$24,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$24,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$24,37*4             ; badAccess
        .syn
        j       loadState

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5	185	hellwig	`.set CIO_CTL,0x00 ; set console to keyboard/display`
6			`; .set CIO_CTL,0x03 ; set console to serial line 0`
7
8	16	hellwig	`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
9	50	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
10	16	hellwig
11			`.set PSW,0 ; reg # of PSW`
12	50	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
13			`.set V,1 << V_SHIFT`
14
15	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
16			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
17			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
18			`.set TLB_ENTRIES,32 ; number of TLB entries`
19	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
20	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
21	16	hellwig
22	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
23	16	hellwig
24	50	hellwig	`.set BIO_OUT,0xF1000000 ; board I/O output port`
25			`.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit`
26
27	16	hellwig	`;***************************************************************`
28
29			`.import _ecode`
30			`.import _edata`
31			`.import _ebss`
32
33	185	hellwig	`.import kbdinit`
34			`.import kbdinchk`
35			`.import kbdin`
36
37	182	hellwig	`.import dspinit`
38			`.import dspoutchk`
39			`.import dspout`
40
41			`.import ser0init`
42	16	hellwig	`.import ser0inchk`
43			`.import ser0in`
44			`.import ser0outchk`
45			`.import ser0out`
46
47	182	hellwig	`.import ser1init`
48			`.import ser1inchk`
49			`.import ser1in`
50			`.import ser1outchk`
51			`.import ser1out`
52	16	hellwig
53	184	hellwig	`.import dskinitctl`
54	182	hellwig	`.import dskcapctl`
55			`.import dskioctl`
56	184	hellwig
57			`.import dskinitser`
58	182	hellwig	`.import dskcapser`
59			`.import dskioser`
60
61	16	hellwig	`.import main`
62
63			`.export _bcode`
64			`.export _bdata`
65			`.export _bbss`
66
67	185	hellwig	`.export setcon`
68	16	hellwig	`.export cinchk`
69			`.export cin`
70			`.export coutchk`
71			`.export cout`
72			`.export dskcap`
73			`.export dskio`
74
75			`.export getTLB_HI`
76			`.export getTLB_LO`
77			`.export setTLB`
78
79			`.export saveState`
80			`.export monitorReturn`
81
82			`.import userContext`
83			`.export resume`
84
85			`;***************************************************************`
86
87			`.code`
88			`_bcode:`
89
90			`.data`
91			`_bdata:`
92
93			`.bss`
94			`_bbss:`
95
96			`;***************************************************************`
97
98			`.code`
99			`.align 4`
100
101	185	hellwig	`startup:`
102	16	hellwig	`j start`
103
104			`interrupt:`
105	200	hellwig	`j debug`
106	16	hellwig
107			`userMiss:`
108	200	hellwig	`j debug`
109	16	hellwig
110	200	hellwig	`monitor:`
111			`j debug`
112
113	16	hellwig	`;***************************************************************`
114
115			`.code`
116			`.align 4`
117
118	185	hellwig	`setcon:`
119			`j setcio`
120
121	16	hellwig	`cinchk:`
122	185	hellwig	`j cichk`
123	16	hellwig
124			`cin:`
125	185	hellwig	`j ci`
126	16	hellwig
127			`coutchk:`
128	185	hellwig	`j cochk`
129	16	hellwig
130			`cout:`
131	185	hellwig	`j co`
132	16	hellwig
133			`dskcap:`
134			`j dcap`
135
136			`dskio:`
137			`j dio`
138
139	200	hellwig	`reserved_11:`
140			`j reserved_11`
141	50	hellwig
142	200	hellwig	`reserved_12:`
143			`j reserved_12`
144	50	hellwig
145	200	hellwig	`reserved_13:`
146			`j reserved_13`
147	50	hellwig
148	200	hellwig	`reserved_14:`
149			`j reserved_14`
150	185	hellwig
151	200	hellwig	`reserved_15:`
152			`j reserved_15`
153	185	hellwig
154	16	hellwig	`;***************************************************************`
155
156			`.code`
157			`.align 4`
158
159			`start:`
160	50	hellwig	`; let irq/exc vectors point to RAM`
161			`add $8,$0,V`
162			`mvts $8,PSW`
163	16	hellwig
164	50	hellwig	`; disable flash ROM, enable SPI bus`
165			`add $8,$0,BIO_OUT`
166			`add $9,$0,SPI_EN`
167			`stw $9,$8,0`
168
169	16	hellwig	`; initialize TLB`
170			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
171			`add $8,$0,dmapaddr ; by impossible virtual page number`
172	182	hellwig	`mvts $8,TLB_ENTRY_HI`
173			`add $8,$0,$0`
174			`add $9,$0,TLB_ENTRIES`
175	16	hellwig	`tlbloop:`
176	182	hellwig	`mvts $8,TLB_INDEX`
177	16	hellwig	`tbwi`
178	182	hellwig	`add $8,$8,1`
179			`bne $8,$9,tlbloop`
180	16	hellwig
181			`; copy data segment`
182			`add $10,$0,_bdata ; lowest dst addr to be written to`
183			`add $8,$0,_edata ; one above the top dst addr`
184			`sub $9,$8,$10 ; $9 = size of data segment`
185			`add $9,$9,_ecode ; data is waiting right after code`
186			`j cpytest`
187			`cpyloop:`
188			`ldw $11,$9,0 ; src addr in $9`
189			`stw $11,$8,0 ; dst addr in $8`
190			`cpytest:`
191			`sub $8,$8,4 ; downward`
192			`sub $9,$9,4`
193			`bgeu $8,$10,cpyloop`
194
195			`; clear bss segment`
196			`add $8,$0,_bbss ; start with first word of bss`
197			`add $9,$0,_ebss ; this is one above the top`
198			`j clrtest`
199			`clrloop:`
200			`stw $0,$8,0 ; dst addr in $8`
201			`add $8,$8,4 ; upward`
202			`clrtest:`
203			`bltu $8,$9,clrloop`
204
205	185	hellwig	`; initialize I/O`
206	16	hellwig	`add $29,$0,stacktop ; setup monitor stack`
207	185	hellwig	`jal kbdinit ; init keyboard`
208	16	hellwig	`jal dspinit ; init display`
209	182	hellwig	`jal ser0init ; init serial line 0`
210			`jal ser1init ; init serial line 1`
211	184	hellwig	`jal dskinitctl ; init disk (controller)`
212			`jal dskinitser ; init disk (serial line)`
213	185	hellwig	`add $4,$0,CIO_CTL ; set console`
214			`jal setcio`
215
216			`; call main`
217	16	hellwig	`jal main ; enter command loop`
218
219			`; main should never return`
220			`j start ; just to be sure...`
221
222			`;***************************************************************`
223
224	50	hellwig	`.code`
225			`.align 4`
226
227	16	hellwig	`; Word getTLB_HI(int index)`
228			`getTLB_HI:`
229			`mvts $4,TLB_INDEX`
230			`tbri`
231			`mvfs $2,TLB_ENTRY_HI`
232			`jr $31`
233
234			`; Word getTLB_LO(int index)`
235			`getTLB_LO:`
236			`mvts $4,TLB_INDEX`
237			`tbri`
238			`mvfs $2,TLB_ENTRY_LO`
239			`jr $31`
240
241			`; void setTLB(int index, Word entryHi, Word entryLo)`
242			`setTLB:`
243			`mvts $4,TLB_INDEX`
244			`mvts $5,TLB_ENTRY_HI`
245			`mvts $6,TLB_ENTRY_LO`
246			`tbwi`
247			`jr $31`
248
249			`;***************************************************************`
250
251	185	hellwig	`.data`
252			`.align 4`
253
254			`cioctl:`
255			`.byte 0`
256
257	50	hellwig	`.code`
258			`.align 4`
259
260	185	hellwig	`; void setcon(Byte ctl)`
261			`setcio:`
262			`stb $4,$0,cioctl`
263			`j $31`
264
265			`; int cinchk(void)`
266			`cichk:`
267			`ldbu $8,$0,cioctl`
268			`and $8,$8,0x01`
269			`bne $8,$0,cichk1`
270			`j kbdinchk`
271			`cichk1:`
272			`j ser0inchk`
273
274			`; char cin(void)`
275			`ci:`
276			`ldbu $8,$0,cioctl`
277			`and $8,$8,0x01`
278			`bne $8,$0,ci1`
279			`j kbdin`
280			`ci1:`
281			`j ser0in`
282
283			`; int coutchk(void)`
284			`cochk:`
285			`ldbu $8,$0,cioctl`
286			`and $8,$8,0x02`
287			`bne $8,$0,cochk1`
288			`j dspoutchk`
289			`cochk1:`
290			`j ser0outchk`
291
292			`; void cout(char c)`
293			`co:`
294			`ldbu $8,$0,cioctl`
295			`and $8,$8,0x02`
296			`bne $8,$0,co1`
297			`j dspout`
298			`co1:`
299			`j ser0out`
300
301			`;***************************************************************`
302
303			`.code`
304			`.align 4`
305
306	16	hellwig	`; int dskcap(int dskno)`
307			`dcap:`
308			`bne $4,$0,dcapser`
309	182	hellwig	`j dskcapctl`
310	16	hellwig	`dcapser:`
311	182	hellwig	`j dskcapser`
312	16	hellwig
313			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
314			`dio:`
315			`bne $4,$0,dioser`
316			`add $4,$5,$0`
317			`add $5,$6,$0`
318			`add $6,$7,$0`
319			`ldw $7,$29,16`
320	182	hellwig	`j dskioctl`
321	16	hellwig	`dioser:`
322			`add $4,$5,$0`
323			`add $5,$6,$0`
324			`add $6,$7,$0`
325			`ldw $7,$29,16`
326	182	hellwig	`j dskioser`
327	16	hellwig
328			`;***************************************************************`
329
330			`.code`
331			`.align 4`
332
333			`; Bool saveState(MonitorState *msp)`
334			`; always return 'true' here`
335			`saveState:`
336			`stw $31,$4,0*4 ; return address`
337			`stw $29,$4,1*4 ; stack pointer`
338			`stw $16,$4,2*4 ; local variables`
339			`stw $17,$4,3*4`
340			`stw $18,$4,4*4`
341			`stw $19,$4,5*4`
342			`stw $20,$4,6*4`
343			`stw $21,$4,7*4`
344			`stw $22,$4,8*4`
345			`stw $23,$4,9*4`
346			`add $2,$0,1`
347			`jr $31`
348
349			`; load state when re-entering monitor`
350			`; this appears as if returning from saveState`
351			`; but the return value is 'false' here`
352			`loadState:`
353			`ldw $8,$0,monitorReturn`
354			`beq $8,$0,loadState ; fatal error: monitor state lost`
355			`ldw $31,$8,0*4 ; return address`
356			`ldw $29,$8,1*4 ; stack pointer`
357			`ldw $16,$8,2*4 ; local variables`
358			`ldw $17,$8,3*4`
359			`ldw $18,$8,4*4`
360			`ldw $19,$8,5*4`
361			`ldw $20,$8,6*4`
362			`ldw $21,$8,7*4`
363			`ldw $22,$8,8*4`
364			`ldw $23,$8,9*4`
365			`add $2,$0,0`
366			`jr $31`
367
368			`.bss`
369			`.align 4`
370
371			`; extern MonitorState *monitorReturn`
372			`monitorReturn:`
373			`.space 4`
374
375			`; extern UserContext userContext`
376			`userContext:`
377			`.space USER_CONTEXT_SIZE`
378
379			`;***************************************************************`
380
381			`.code`
382			`.align 4`
383
384			`; void resume(void)`
385			`; use userContext to load state`
386			`resume:`
387			`mvts $0,PSW`
388	201	hellwig	`add $24,$0,userContext`
389	16	hellwig	`.nosyn`
390	201	hellwig	`ldw $8,$24,33*4 ; tlbIndex`
391	16	hellwig	`mvts $8,TLB_INDEX`
392	201	hellwig	`ldw $8,$24,34*4 ; tlbEntryHi`
393	16	hellwig	`mvts $8,TLB_ENTRY_HI`
394	201	hellwig	`ldw $8,$24,35*4 ; tlbEntryLo`
395	16	hellwig	`mvts $8,TLB_ENTRY_LO`
396	201	hellwig	`ldw $8,$24,36*4 ; badAddress`
397	84	hellwig	`mvts $8,BAD_ADDRESS`
398	201	hellwig	`ldw $8,$24,37*4 ; badAccess`
399	180	hellwig	`mvts $8,BAD_ACCESS`
400	201	hellwig	`;ldw $0,$24,0*4 ; registers`
401			`ldw $1,$24,1*4`
402			`ldw $2,$24,2*4`
403			`ldw $3,$24,3*4`
404			`ldw $4,$24,4*4`
405			`ldw $5,$24,5*4`
406			`ldw $6,$24,6*4`
407			`ldw $7,$24,7*4`
408			`ldw $8,$24,8*4`
409			`ldw $9,$24,9*4`
410			`ldw $10,$24,10*4`
411			`ldw $11,$24,11*4`
412			`ldw $12,$24,12*4`
413			`ldw $13,$24,13*4`
414			`ldw $14,$24,14*4`
415			`ldw $15,$24,15*4`
416			`ldw $16,$24,16*4`
417			`ldw $17,$24,17*4`
418			`ldw $18,$24,18*4`
419			`ldw $19,$24,19*4`
420			`ldw $20,$24,20*4`
421			`ldw $21,$24,21*4`
422			`ldw $22,$24,22*4`
423			`ldw $23,$24,23*4`
424			`;ldw $24,$24,24*4`
425			`ldw $25,$24,25*4`
426			`ldw $26,$24,26*4`
427			`ldw $27,$24,27*4`
428			`ldw $28,$24,28*4`
429			`ldw $29,$24,29*4`
430			`ldw $30,$24,30*4`
431			`ldw $31,$24,31*4`
432			`ldw $24,$24,32*4 ; psw`
433			`mvts $24,PSW`
434	16	hellwig	`rfx`
435			`.syn`
436
437	200	hellwig	`; debug entry`
438	16	hellwig	`; use userContext to store state`
439	200	hellwig	`debug:`
440	16	hellwig	`.nosyn`
441	201	hellwig	`ldhi $24,userContext`
442			`or $24,$24,userContext`
443			`stw $0,$24,0*4 ; registers`
444			`stw $1,$24,1*4`
445			`stw $2,$24,2*4`
446			`stw $3,$24,3*4`
447			`stw $4,$24,4*4`
448			`stw $5,$24,5*4`
449			`stw $6,$24,6*4`
450			`stw $7,$24,7*4`
451			`stw $8,$24,8*4`
452			`stw $9,$24,9*4`
453			`stw $10,$24,10*4`
454			`stw $11,$24,11*4`
455			`stw $12,$24,12*4`
456			`stw $13,$24,13*4`
457			`stw $14,$24,14*4`
458			`stw $15,$24,15*4`
459			`stw $16,$24,16*4`
460			`stw $17,$24,17*4`
461			`stw $18,$24,18*4`
462			`stw $19,$24,19*4`
463			`stw $20,$24,20*4`
464			`stw $21,$24,21*4`
465			`stw $22,$24,22*4`
466			`stw $23,$24,23*4`
467			`stw $24,$24,24*4`
468			`stw $25,$24,25*4`
469			`stw $26,$24,26*4`
470			`stw $27,$24,27*4`
471			`stw $28,$24,28*4`
472			`stw $29,$24,29*4`
473			`stw $30,$24,30*4`
474			`stw $31,$24,31*4`
475	16	hellwig	`mvfs $8,PSW`
476	201	hellwig	`stw $8,$24,32*4 ; psw`
477	16	hellwig	`mvfs $8,TLB_INDEX`
478	201	hellwig	`stw $8,$24,33*4 ; tlbIndex`
479	16	hellwig	`mvfs $8,TLB_ENTRY_HI`
480	201	hellwig	`stw $8,$24,34*4 ; tlbEntryHi`
481	16	hellwig	`mvfs $8,TLB_ENTRY_LO`
482	201	hellwig	`stw $8,$24,35*4 ; tlbEntryLo`
483	84	hellwig	`mvfs $8,BAD_ADDRESS`
484	201	hellwig	`stw $8,$24,36*4 ; badAddress`
485	180	hellwig	`mvfs $8,BAD_ACCESS`
486	201	hellwig	`stw $8,$24,37*4 ; badAccess`
487	16	hellwig	`.syn`
488			`j loadState`

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