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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [s3e-500/] [start.s] - Blame information for rev 262

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    BIO_BASE,0xF1000000     ; board I/O base address
        .set    BIO_WR,BIO_BASE+0
        .set    SPI_EN,0x80000000       ; SPI bus enable ctrl bit
        .set    BIO_RD,BIO_BASE+4
        .set    CIO_CTRL,0x08           ; this bit controls console I/O
 
        .set    CIO_KBD_DSP,0x00        ; set console to keyboard/display
        .set    CIO_SERIAL_0,0x03       ; set console to serial line 0
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import ser0init
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import ser1init
        .import ser1inchk
        .import ser1in
        .import ser1outchk
        .import ser1out
 
        .import dskinitctl
        .import dskcapctl
        .import dskioctl
 
        .import dskinitser
        .import dskcapser
        .import dskioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export setcon
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
startup:
        j       start
 
interrupt:
        j       debug
 
userMiss:
        j       debug
 
monitor:
        j       debug
 
;***************************************************************
 
        .code
        .align  4
 
setcon:
        j       setcio
 
cinchk:
        j       cichk
 
cin:
        j       ci
 
coutchk:
        j       cochk
 
cout:
        j       co
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved_11:
        j       reserved_11
 
reserved_12:
        j       reserved_12
 
reserved_13:
        j       reserved_13
 
reserved_14:
        j       reserved_14
 
reserved_15:
        j       reserved_15
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; disable flash ROM, enable SPI bus
        add     $8,$0,BIO_WR
        add     $9,$0,SPI_EN
        stw     $9,$8,0
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        mvts    $8,TLB_ENTRY_HI
        add     $8,$0,$0
        add     $9,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_INDEX
        tbwi
        add     $8,$8,1
        bne     $8,$9,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; initialize I/O
        add     $29,$0,stacktop          ; setup monitor stack
        jal     kbdinit                 ; init keyboard
        jal     dspinit                 ; init display
        jal     ser0init                ; init serial line 0
        jal     ser1init                ; init serial line 1
        jal     dskinitctl              ; init disk (controller)
        jal     dskinitser              ; init disk (serial line)
        ldw     $8,$0,BIO_RD             ; get switch settings
        and     $8,$8,CIO_CTRL
        add     $4,$0,CIO_SERIAL_0       ; set console to serial line
        bne     $8,$0,swtchset
        add     $4,$0,CIO_KBD_DSP        ; set console to kbd/dsp
swtchset:
        jal     setcio
 
        ; call main
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .data
        .align  4
 
cioctl:
        .byte   0
 
        .code
        .align  4
 
        ; void setcon(Byte ctl)
setcio:
        stb     $4,$0,cioctl
        j       $31
 
        ; int cinchk(void)
cichk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,cichk1
        j       kbdinchk
cichk1:
        j       ser0inchk
 
        ; char cin(void)
ci:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,ci1
        j       kbdin
ci1:
        j       ser0in
 
        ; int coutchk(void)
cochk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,cochk1
        j       dspoutchk
cochk1:
        j       ser0outchk
 
        ; void cout(char c)
co:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,co1
        j       dspout
co1:
        j       ser0out
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       dskcapctl
dcapser:
        j       dskcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $24,$0,userContext
        .nosyn
        ldw     $8,$24,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$24,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$24,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$24,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$24,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$24,0*4              ; registers
        ldw     $1,$24,1*4
        ldw     $2,$24,2*4
        ldw     $3,$24,3*4
        ldw     $4,$24,4*4
        ldw     $5,$24,5*4
        ldw     $6,$24,6*4
        ldw     $7,$24,7*4
        ldw     $8,$24,8*4
        ldw     $9,$24,9*4
        ldw     $10,$24,10*4
        ldw     $11,$24,11*4
        ldw     $12,$24,12*4
        ldw     $13,$24,13*4
        ldw     $14,$24,14*4
        ldw     $15,$24,15*4
        ldw     $16,$24,16*4
        ldw     $17,$24,17*4
        ldw     $18,$24,18*4
        ldw     $19,$24,19*4
        ldw     $20,$24,20*4
        ldw     $21,$24,21*4
        ldw     $22,$24,22*4
        ldw     $23,$24,23*4
        ;ldw    $24,$24,24*4
        ldw     $25,$24,25*4
        ldw     $26,$24,26*4
        ldw     $27,$24,27*4
        ldw     $28,$24,28*4
        ldw     $29,$24,29*4
        ldw     $30,$24,30*4
        ldw     $31,$24,31*4
        ldw     $24,$24,32*4            ; psw
        mvts    $24,PSW
        rfx
        .syn
 
        ; debug entry
        ; use userContext to store state
debug:
        .nosyn
        ldhi    $24,userContext
        or      $24,$24,userContext
        stw     $0,$24,0*4                ; registers
        stw     $1,$24,1*4
        stw     $2,$24,2*4
        stw     $3,$24,3*4
        stw     $4,$24,4*4
        stw     $5,$24,5*4
        stw     $6,$24,6*4
        stw     $7,$24,7*4
        stw     $8,$24,8*4
        stw     $9,$24,9*4
        stw     $10,$24,10*4
        stw     $11,$24,11*4
        stw     $12,$24,12*4
        stw     $13,$24,13*4
        stw     $14,$24,14*4
        stw     $15,$24,15*4
        stw     $16,$24,16*4
        stw     $17,$24,17*4
        stw     $18,$24,18*4
        stw     $19,$24,19*4
        stw     $20,$24,20*4
        stw     $21,$24,21*4
        stw     $22,$24,22*4
        stw     $23,$24,23*4
        stw     $24,$24,24*4
        stw     $25,$24,25*4
        stw     $26,$24,26*4
        stw     $27,$24,27*4
        stw     $28,$24,28*4
        stw     $29,$24,29*4
        stw     $30,$24,30*4
        stw     $31,$24,31*4
        mvfs    $8,PSW
        stw     $8,$24,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$24,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$24,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$24,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$24,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$24,37*4             ; badAccess
        .syn
        j       loadState

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5	242	hellwig	`.set BIO_BASE,0xF1000000 ; board I/O base address`
6			`.set BIO_WR,BIO_BASE+0`
7			`.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit`
8			`.set BIO_RD,BIO_BASE+4`
9			`.set CIO_CTRL,0x08 ; this bit controls console I/O`
10	185	hellwig
11	242	hellwig	`.set CIO_KBD_DSP,0x00 ; set console to keyboard/display`
12			`.set CIO_SERIAL_0,0x03 ; set console to serial line 0`
13
14	16	hellwig	`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
15	50	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
16	16	hellwig
17			`.set PSW,0 ; reg # of PSW`
18	50	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
19			`.set V,1 << V_SHIFT`
20
21	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
22			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
23			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
24			`.set TLB_ENTRIES,32 ; number of TLB entries`
25	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
26	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
27	16	hellwig
28	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
29	16	hellwig
30			`;***************************************************************`
31
32			`.import _ecode`
33			`.import _edata`
34			`.import _ebss`
35
36	185	hellwig	`.import kbdinit`
37			`.import kbdinchk`
38			`.import kbdin`
39
40	182	hellwig	`.import dspinit`
41			`.import dspoutchk`
42			`.import dspout`
43
44			`.import ser0init`
45	16	hellwig	`.import ser0inchk`
46			`.import ser0in`
47			`.import ser0outchk`
48			`.import ser0out`
49
50	182	hellwig	`.import ser1init`
51			`.import ser1inchk`
52			`.import ser1in`
53			`.import ser1outchk`
54			`.import ser1out`
55	16	hellwig
56	184	hellwig	`.import dskinitctl`
57	182	hellwig	`.import dskcapctl`
58			`.import dskioctl`
59	184	hellwig
60			`.import dskinitser`
61	182	hellwig	`.import dskcapser`
62			`.import dskioser`
63
64	16	hellwig	`.import main`
65
66			`.export _bcode`
67			`.export _bdata`
68			`.export _bbss`
69
70	185	hellwig	`.export setcon`
71	16	hellwig	`.export cinchk`
72			`.export cin`
73			`.export coutchk`
74			`.export cout`
75			`.export dskcap`
76			`.export dskio`
77
78			`.export getTLB_HI`
79			`.export getTLB_LO`
80			`.export setTLB`
81
82			`.export saveState`
83			`.export monitorReturn`
84
85			`.import userContext`
86			`.export resume`
87
88			`;***************************************************************`
89
90			`.code`
91			`_bcode:`
92
93			`.data`
94			`_bdata:`
95
96			`.bss`
97			`_bbss:`
98
99			`;***************************************************************`
100
101			`.code`
102			`.align 4`
103
104	185	hellwig	`startup:`
105	16	hellwig	`j start`
106
107			`interrupt:`
108	200	hellwig	`j debug`
109	16	hellwig
110			`userMiss:`
111	200	hellwig	`j debug`
112	16	hellwig
113	200	hellwig	`monitor:`
114			`j debug`
115
116	16	hellwig	`;***************************************************************`
117
118			`.code`
119			`.align 4`
120
121	185	hellwig	`setcon:`
122			`j setcio`
123
124	16	hellwig	`cinchk:`
125	185	hellwig	`j cichk`
126	16	hellwig
127			`cin:`
128	185	hellwig	`j ci`
129	16	hellwig
130			`coutchk:`
131	185	hellwig	`j cochk`
132	16	hellwig
133			`cout:`
134	185	hellwig	`j co`
135	16	hellwig
136			`dskcap:`
137			`j dcap`
138
139			`dskio:`
140			`j dio`
141
142	200	hellwig	`reserved_11:`
143			`j reserved_11`
144	50	hellwig
145	200	hellwig	`reserved_12:`
146			`j reserved_12`
147	50	hellwig
148	200	hellwig	`reserved_13:`
149			`j reserved_13`
150	50	hellwig
151	200	hellwig	`reserved_14:`
152			`j reserved_14`
153	185	hellwig
154	200	hellwig	`reserved_15:`
155			`j reserved_15`
156	185	hellwig
157	16	hellwig	`;***************************************************************`
158
159			`.code`
160			`.align 4`
161
162			`start:`
163	50	hellwig	`; let irq/exc vectors point to RAM`
164			`add $8,$0,V`
165			`mvts $8,PSW`
166	16	hellwig
167	50	hellwig	`; disable flash ROM, enable SPI bus`
168	242	hellwig	`add $8,$0,BIO_WR`
169	50	hellwig	`add $9,$0,SPI_EN`
170			`stw $9,$8,0`
171
172	16	hellwig	`; initialize TLB`
173			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
174			`add $8,$0,dmapaddr ; by impossible virtual page number`
175	182	hellwig	`mvts $8,TLB_ENTRY_HI`
176			`add $8,$0,$0`
177			`add $9,$0,TLB_ENTRIES`
178	16	hellwig	`tlbloop:`
179	182	hellwig	`mvts $8,TLB_INDEX`
180	16	hellwig	`tbwi`
181	182	hellwig	`add $8,$8,1`
182			`bne $8,$9,tlbloop`
183	16	hellwig
184			`; copy data segment`
185			`add $10,$0,_bdata ; lowest dst addr to be written to`
186			`add $8,$0,_edata ; one above the top dst addr`
187			`sub $9,$8,$10 ; $9 = size of data segment`
188			`add $9,$9,_ecode ; data is waiting right after code`
189			`j cpytest`
190			`cpyloop:`
191			`ldw $11,$9,0 ; src addr in $9`
192			`stw $11,$8,0 ; dst addr in $8`
193			`cpytest:`
194			`sub $8,$8,4 ; downward`
195			`sub $9,$9,4`
196			`bgeu $8,$10,cpyloop`
197
198			`; clear bss segment`
199			`add $8,$0,_bbss ; start with first word of bss`
200			`add $9,$0,_ebss ; this is one above the top`
201			`j clrtest`
202			`clrloop:`
203			`stw $0,$8,0 ; dst addr in $8`
204			`add $8,$8,4 ; upward`
205			`clrtest:`
206			`bltu $8,$9,clrloop`
207
208	185	hellwig	`; initialize I/O`
209	16	hellwig	`add $29,$0,stacktop ; setup monitor stack`
210	185	hellwig	`jal kbdinit ; init keyboard`
211	16	hellwig	`jal dspinit ; init display`
212	182	hellwig	`jal ser0init ; init serial line 0`
213			`jal ser1init ; init serial line 1`
214	184	hellwig	`jal dskinitctl ; init disk (controller)`
215			`jal dskinitser ; init disk (serial line)`
216	242	hellwig	`ldw $8,$0,BIO_RD ; get switch settings`
217			`and $8,$8,CIO_CTRL`
218			`add $4,$0,CIO_SERIAL_0 ; set console to serial line`
219			`bne $8,$0,swtchset`
220			`add $4,$0,CIO_KBD_DSP ; set console to kbd/dsp`
221			`swtchset:`
222	185	hellwig	`jal setcio`
223
224			`; call main`
225	16	hellwig	`jal main ; enter command loop`
226
227			`; main should never return`
228			`j start ; just to be sure...`
229
230			`;***************************************************************`
231
232	50	hellwig	`.code`
233			`.align 4`
234
235	16	hellwig	`; Word getTLB_HI(int index)`
236			`getTLB_HI:`
237			`mvts $4,TLB_INDEX`
238			`tbri`
239			`mvfs $2,TLB_ENTRY_HI`
240			`jr $31`
241
242			`; Word getTLB_LO(int index)`
243			`getTLB_LO:`
244			`mvts $4,TLB_INDEX`
245			`tbri`
246			`mvfs $2,TLB_ENTRY_LO`
247			`jr $31`
248
249			`; void setTLB(int index, Word entryHi, Word entryLo)`
250			`setTLB:`
251			`mvts $4,TLB_INDEX`
252			`mvts $5,TLB_ENTRY_HI`
253			`mvts $6,TLB_ENTRY_LO`
254			`tbwi`
255			`jr $31`
256
257			`;***************************************************************`
258
259	185	hellwig	`.data`
260			`.align 4`
261
262			`cioctl:`
263			`.byte 0`
264
265	50	hellwig	`.code`
266			`.align 4`
267
268	185	hellwig	`; void setcon(Byte ctl)`
269			`setcio:`
270			`stb $4,$0,cioctl`
271			`j $31`
272
273			`; int cinchk(void)`
274			`cichk:`
275			`ldbu $8,$0,cioctl`
276			`and $8,$8,0x01`
277			`bne $8,$0,cichk1`
278			`j kbdinchk`
279			`cichk1:`
280			`j ser0inchk`
281
282			`; char cin(void)`
283			`ci:`
284			`ldbu $8,$0,cioctl`
285			`and $8,$8,0x01`
286			`bne $8,$0,ci1`
287			`j kbdin`
288			`ci1:`
289			`j ser0in`
290
291			`; int coutchk(void)`
292			`cochk:`
293			`ldbu $8,$0,cioctl`
294			`and $8,$8,0x02`
295			`bne $8,$0,cochk1`
296			`j dspoutchk`
297			`cochk1:`
298			`j ser0outchk`
299
300			`; void cout(char c)`
301			`co:`
302			`ldbu $8,$0,cioctl`
303			`and $8,$8,0x02`
304			`bne $8,$0,co1`
305			`j dspout`
306			`co1:`
307			`j ser0out`
308
309			`;***************************************************************`
310
311			`.code`
312			`.align 4`
313
314	16	hellwig	`; int dskcap(int dskno)`
315			`dcap:`
316			`bne $4,$0,dcapser`
317	182	hellwig	`j dskcapctl`
318	16	hellwig	`dcapser:`
319	182	hellwig	`j dskcapser`
320	16	hellwig
321			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
322			`dio:`
323			`bne $4,$0,dioser`
324			`add $4,$5,$0`
325			`add $5,$6,$0`
326			`add $6,$7,$0`
327			`ldw $7,$29,16`
328	182	hellwig	`j dskioctl`
329	16	hellwig	`dioser:`
330			`add $4,$5,$0`
331			`add $5,$6,$0`
332			`add $6,$7,$0`
333			`ldw $7,$29,16`
334	182	hellwig	`j dskioser`
335	16	hellwig
336			`;***************************************************************`
337
338			`.code`
339			`.align 4`
340
341			`; Bool saveState(MonitorState *msp)`
342			`; always return 'true' here`
343			`saveState:`
344			`stw $31,$4,0*4 ; return address`
345			`stw $29,$4,1*4 ; stack pointer`
346			`stw $16,$4,2*4 ; local variables`
347			`stw $17,$4,3*4`
348			`stw $18,$4,4*4`
349			`stw $19,$4,5*4`
350			`stw $20,$4,6*4`
351			`stw $21,$4,7*4`
352			`stw $22,$4,8*4`
353			`stw $23,$4,9*4`
354			`add $2,$0,1`
355			`jr $31`
356
357			`; load state when re-entering monitor`
358			`; this appears as if returning from saveState`
359			`; but the return value is 'false' here`
360			`loadState:`
361			`ldw $8,$0,monitorReturn`
362			`beq $8,$0,loadState ; fatal error: monitor state lost`
363			`ldw $31,$8,0*4 ; return address`
364			`ldw $29,$8,1*4 ; stack pointer`
365			`ldw $16,$8,2*4 ; local variables`
366			`ldw $17,$8,3*4`
367			`ldw $18,$8,4*4`
368			`ldw $19,$8,5*4`
369			`ldw $20,$8,6*4`
370			`ldw $21,$8,7*4`
371			`ldw $22,$8,8*4`
372			`ldw $23,$8,9*4`
373			`add $2,$0,0`
374			`jr $31`
375
376			`.bss`
377			`.align 4`
378
379			`; extern MonitorState *monitorReturn`
380			`monitorReturn:`
381			`.space 4`
382
383			`; extern UserContext userContext`
384			`userContext:`
385			`.space USER_CONTEXT_SIZE`
386
387			`;***************************************************************`
388
389			`.code`
390			`.align 4`
391
392			`; void resume(void)`
393			`; use userContext to load state`
394			`resume:`
395			`mvts $0,PSW`
396	201	hellwig	`add $24,$0,userContext`
397	16	hellwig	`.nosyn`
398	201	hellwig	`ldw $8,$24,33*4 ; tlbIndex`
399	16	hellwig	`mvts $8,TLB_INDEX`
400	201	hellwig	`ldw $8,$24,34*4 ; tlbEntryHi`
401	16	hellwig	`mvts $8,TLB_ENTRY_HI`
402	201	hellwig	`ldw $8,$24,35*4 ; tlbEntryLo`
403	16	hellwig	`mvts $8,TLB_ENTRY_LO`
404	201	hellwig	`ldw $8,$24,36*4 ; badAddress`
405	84	hellwig	`mvts $8,BAD_ADDRESS`
406	201	hellwig	`ldw $8,$24,37*4 ; badAccess`
407	180	hellwig	`mvts $8,BAD_ACCESS`
408	201	hellwig	`;ldw $0,$24,0*4 ; registers`
409			`ldw $1,$24,1*4`
410			`ldw $2,$24,2*4`
411			`ldw $3,$24,3*4`
412			`ldw $4,$24,4*4`
413			`ldw $5,$24,5*4`
414			`ldw $6,$24,6*4`
415			`ldw $7,$24,7*4`
416			`ldw $8,$24,8*4`
417			`ldw $9,$24,9*4`
418			`ldw $10,$24,10*4`
419			`ldw $11,$24,11*4`
420			`ldw $12,$24,12*4`
421			`ldw $13,$24,13*4`
422			`ldw $14,$24,14*4`
423			`ldw $15,$24,15*4`
424			`ldw $16,$24,16*4`
425			`ldw $17,$24,17*4`
426			`ldw $18,$24,18*4`
427			`ldw $19,$24,19*4`
428			`ldw $20,$24,20*4`
429			`ldw $21,$24,21*4`
430			`ldw $22,$24,22*4`
431			`ldw $23,$24,23*4`
432			`;ldw $24,$24,24*4`
433			`ldw $25,$24,25*4`
434			`ldw $26,$24,26*4`
435			`ldw $27,$24,27*4`
436			`ldw $28,$24,28*4`
437			`ldw $29,$24,29*4`
438			`ldw $30,$24,30*4`
439			`ldw $31,$24,31*4`
440			`ldw $24,$24,32*4 ; psw`
441			`mvts $24,PSW`
442	16	hellwig	`rfx`
443			`.syn`
444
445	200	hellwig	`; debug entry`
446	16	hellwig	`; use userContext to store state`
447	200	hellwig	`debug:`
448	16	hellwig	`.nosyn`
449	201	hellwig	`ldhi $24,userContext`
450			`or $24,$24,userContext`
451			`stw $0,$24,0*4 ; registers`
452			`stw $1,$24,1*4`
453			`stw $2,$24,2*4`
454			`stw $3,$24,3*4`
455			`stw $4,$24,4*4`
456			`stw $5,$24,5*4`
457			`stw $6,$24,6*4`
458			`stw $7,$24,7*4`
459			`stw $8,$24,8*4`
460			`stw $9,$24,9*4`
461			`stw $10,$24,10*4`
462			`stw $11,$24,11*4`
463			`stw $12,$24,12*4`
464			`stw $13,$24,13*4`
465			`stw $14,$24,14*4`
466			`stw $15,$24,15*4`
467			`stw $16,$24,16*4`
468			`stw $17,$24,17*4`
469			`stw $18,$24,18*4`
470			`stw $19,$24,19*4`
471			`stw $20,$24,20*4`
472			`stw $21,$24,21*4`
473			`stw $22,$24,22*4`
474			`stw $23,$24,23*4`
475			`stw $24,$24,24*4`
476			`stw $25,$24,25*4`
477			`stw $26,$24,26*4`
478			`stw $27,$24,27*4`
479			`stw $28,$24,28*4`
480			`stw $29,$24,29*4`
481			`stw $30,$24,30*4`
482			`stw $31,$24,31*4`
483	16	hellwig	`mvfs $8,PSW`
484	201	hellwig	`stw $8,$24,32*4 ; psw`
485	16	hellwig	`mvfs $8,TLB_INDEX`
486	201	hellwig	`stw $8,$24,33*4 ; tlbIndex`
487	16	hellwig	`mvfs $8,TLB_ENTRY_HI`
488	201	hellwig	`stw $8,$24,34*4 ; tlbEntryHi`
489	16	hellwig	`mvfs $8,TLB_ENTRY_LO`
490	201	hellwig	`stw $8,$24,35*4 ; tlbEntryLo`
491	84	hellwig	`mvfs $8,BAD_ADDRESS`
492	201	hellwig	`stw $8,$24,36*4 ; badAddress`
493	180	hellwig	`mvfs $8,BAD_ACCESS`
494	201	hellwig	`stw $8,$24,37*4 ; badAccess`
495	16	hellwig	`.syn`
496			`j loadState`

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