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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [simulator/] [start.s] - Blame information for rev 189

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
;       .set    CIO_CTL,0x00            ; set console to keyboard/display
        .set    CIO_CTL,0x03            ; set console to serial line 0
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import ser0init
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import ser1init
        .import ser1inchk
        .import ser1in
        .import ser1outchk
        .import ser1out
 
        .import dskinitctl
        .import dskcapctl
        .import dskioctl
 
        .import dskinitser
        .import dskcapser
        .import dskioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export setcon
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
startup:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
setcon:
        j       setcio
 
cinchk:
        j       cichk
 
cin:
        j       ci
 
coutchk:
        j       cochk
 
cout:
        j       co
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved10:
        j       reserved10
 
reserved11:
        j       reserved11
 
reserved12:
        j       reserved12
 
reserved13:
        j       reserved13
 
reserved14:
        j       reserved14
 
reserved15:
        j       reserved15
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        mvts    $8,TLB_ENTRY_HI
        add     $8,$0,$0
        add     $9,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_INDEX
        tbwi
        add     $8,$8,1
        bne     $8,$9,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; initialize I/O
        add     $29,$0,stacktop          ; setup monitor stack
        jal     kbdinit                 ; init keyboard
        jal     dspinit                 ; init display
        jal     ser0init                ; init serial line 0
        jal     ser1init                ; init serial line 1
        jal     dskinitctl              ; init disk (controller)
        jal     dskinitser              ; init disk (serial line)
        add     $4,$0,CIO_CTL            ; set console
        jal     setcio
 
        ; call main
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .data
        .align  4
 
cioctl:
        .byte   0
 
        .code
        .align  4
 
        ; void setcon(Byte ctl)
setcio:
        stb     $4,$0,cioctl
        j       $31
 
        ; int cinchk(void)
cichk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,cichk1
        j       kbdinchk
cichk1:
        j       ser0inchk
 
        ; char cin(void)
ci:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,ci1
        j       kbdin
ci1:
        j       ser0in
 
        ; int coutchk(void)
cochk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,cochk1
        j       dspoutchk
cochk1:
        j       ser0outchk
 
        ; void cout(char c)
co:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,co1
        j       dspout
co1:
        j       ser0out
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       dskcapctl
dcapser:
        j       dskcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$28,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$28,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$28,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$28,37*4             ; badAccess
        .syn
        j       loadState

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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [simulator/] [start.s] - Blame information for rev 189

Line No.	Rev	Author	Line
1	189	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`; .set CIO_CTL,0x00 ; set console to keyboard/display`
6			`.set CIO_CTL,0x03 ; set console to serial line 0`
7
8			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
9			`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
10
11			`.set PSW,0 ; reg # of PSW`
12			`.set V_SHIFT,27 ; interrupt vector ctrl bit`
13			`.set V,1 << V_SHIFT`
14
15			`.set TLB_INDEX,1 ; reg # of TLB Index`
16			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
17			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
18			`.set TLB_ENTRIES,32 ; number of TLB entries`
19			`.set BAD_ADDRESS,4 ; reg # of bad address reg`
20			`.set BAD_ACCESS,5 ; reg # of bad access reg`
21
22			`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
23
24			`;***************************************************************`
25
26			`.import _ecode`
27			`.import _edata`
28			`.import _ebss`
29
30			`.import kbdinit`
31			`.import kbdinchk`
32			`.import kbdin`
33
34			`.import dspinit`
35			`.import dspoutchk`
36			`.import dspout`
37
38			`.import ser0init`
39			`.import ser0inchk`
40			`.import ser0in`
41			`.import ser0outchk`
42			`.import ser0out`
43
44			`.import ser1init`
45			`.import ser1inchk`
46			`.import ser1in`
47			`.import ser1outchk`
48			`.import ser1out`
49
50			`.import dskinitctl`
51			`.import dskcapctl`
52			`.import dskioctl`
53
54			`.import dskinitser`
55			`.import dskcapser`
56			`.import dskioser`
57
58			`.import main`
59
60			`.export _bcode`
61			`.export _bdata`
62			`.export _bbss`
63
64			`.export setcon`
65			`.export cinchk`
66			`.export cin`
67			`.export coutchk`
68			`.export cout`
69			`.export dskcap`
70			`.export dskio`
71
72			`.export getTLB_HI`
73			`.export getTLB_LO`
74			`.export setTLB`
75
76			`.export saveState`
77			`.export monitorReturn`
78
79			`.import userContext`
80			`.export resume`
81
82			`;***************************************************************`
83
84			`.code`
85			`_bcode:`
86
87			`.data`
88			`_bdata:`
89
90			`.bss`
91			`_bbss:`
92
93			`;***************************************************************`
94
95			`.code`
96			`.align 4`
97
98			`startup:`
99			`j start`
100
101			`interrupt:`
102			`j isr`
103
104			`userMiss:`
105			`j umsr`
106
107			`;***************************************************************`
108
109			`.code`
110			`.align 4`
111
112			`setcon:`
113			`j setcio`
114
115			`cinchk:`
116			`j cichk`
117
118			`cin:`
119			`j ci`
120
121			`coutchk:`
122			`j cochk`
123
124			`cout:`
125			`j co`
126
127			`dskcap:`
128			`j dcap`
129
130			`dskio:`
131			`j dio`
132
133			`reserved10:`
134			`j reserved10`
135
136			`reserved11:`
137			`j reserved11`
138
139			`reserved12:`
140			`j reserved12`
141
142			`reserved13:`
143			`j reserved13`
144
145			`reserved14:`
146			`j reserved14`
147
148			`reserved15:`
149			`j reserved15`
150
151			`;***************************************************************`
152
153			`.code`
154			`.align 4`
155
156			`start:`
157			`; let irq/exc vectors point to RAM`
158			`add $8,$0,V`
159			`mvts $8,PSW`
160
161			`; initialize TLB`
162			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
163			`add $8,$0,dmapaddr ; by impossible virtual page number`
164			`mvts $8,TLB_ENTRY_HI`
165			`add $8,$0,$0`
166			`add $9,$0,TLB_ENTRIES`
167			`tlbloop:`
168			`mvts $8,TLB_INDEX`
169			`tbwi`
170			`add $8,$8,1`
171			`bne $8,$9,tlbloop`
172
173			`; copy data segment`
174			`add $10,$0,_bdata ; lowest dst addr to be written to`
175			`add $8,$0,_edata ; one above the top dst addr`
176			`sub $9,$8,$10 ; $9 = size of data segment`
177			`add $9,$9,_ecode ; data is waiting right after code`
178			`j cpytest`
179			`cpyloop:`
180			`ldw $11,$9,0 ; src addr in $9`
181			`stw $11,$8,0 ; dst addr in $8`
182			`cpytest:`
183			`sub $8,$8,4 ; downward`
184			`sub $9,$9,4`
185			`bgeu $8,$10,cpyloop`
186
187			`; clear bss segment`
188			`add $8,$0,_bbss ; start with first word of bss`
189			`add $9,$0,_ebss ; this is one above the top`
190			`j clrtest`
191			`clrloop:`
192			`stw $0,$8,0 ; dst addr in $8`
193			`add $8,$8,4 ; upward`
194			`clrtest:`
195			`bltu $8,$9,clrloop`
196
197			`; initialize I/O`
198			`add $29,$0,stacktop ; setup monitor stack`
199			`jal kbdinit ; init keyboard`
200			`jal dspinit ; init display`
201			`jal ser0init ; init serial line 0`
202			`jal ser1init ; init serial line 1`
203			`jal dskinitctl ; init disk (controller)`
204			`jal dskinitser ; init disk (serial line)`
205			`add $4,$0,CIO_CTL ; set console`
206			`jal setcio`
207
208			`; call main`
209			`jal main ; enter command loop`
210
211			`; main should never return`
212			`j start ; just to be sure...`
213
214			`;***************************************************************`
215
216			`.code`
217			`.align 4`
218
219			`; Word getTLB_HI(int index)`
220			`getTLB_HI:`
221			`mvts $4,TLB_INDEX`
222			`tbri`
223			`mvfs $2,TLB_ENTRY_HI`
224			`jr $31`
225
226			`; Word getTLB_LO(int index)`
227			`getTLB_LO:`
228			`mvts $4,TLB_INDEX`
229			`tbri`
230			`mvfs $2,TLB_ENTRY_LO`
231			`jr $31`
232
233			`; void setTLB(int index, Word entryHi, Word entryLo)`
234			`setTLB:`
235			`mvts $4,TLB_INDEX`
236			`mvts $5,TLB_ENTRY_HI`
237			`mvts $6,TLB_ENTRY_LO`
238			`tbwi`
239			`jr $31`
240
241			`;***************************************************************`
242
243			`.data`
244			`.align 4`
245
246			`cioctl:`
247			`.byte 0`
248
249			`.code`
250			`.align 4`
251
252			`; void setcon(Byte ctl)`
253			`setcio:`
254			`stb $4,$0,cioctl`
255			`j $31`
256
257			`; int cinchk(void)`
258			`cichk:`
259			`ldbu $8,$0,cioctl`
260			`and $8,$8,0x01`
261			`bne $8,$0,cichk1`
262			`j kbdinchk`
263			`cichk1:`
264			`j ser0inchk`
265
266			`; char cin(void)`
267			`ci:`
268			`ldbu $8,$0,cioctl`
269			`and $8,$8,0x01`
270			`bne $8,$0,ci1`
271			`j kbdin`
272			`ci1:`
273			`j ser0in`
274
275			`; int coutchk(void)`
276			`cochk:`
277			`ldbu $8,$0,cioctl`
278			`and $8,$8,0x02`
279			`bne $8,$0,cochk1`
280			`j dspoutchk`
281			`cochk1:`
282			`j ser0outchk`
283
284			`; void cout(char c)`
285			`co:`
286			`ldbu $8,$0,cioctl`
287			`and $8,$8,0x02`
288			`bne $8,$0,co1`
289			`j dspout`
290			`co1:`
291			`j ser0out`
292
293			`;***************************************************************`
294
295			`.code`
296			`.align 4`
297
298			`; int dskcap(int dskno)`
299			`dcap:`
300			`bne $4,$0,dcapser`
301			`j dskcapctl`
302			`dcapser:`
303			`j dskcapser`
304
305			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
306			`dio:`
307			`bne $4,$0,dioser`
308			`add $4,$5,$0`
309			`add $5,$6,$0`
310			`add $6,$7,$0`
311			`ldw $7,$29,16`
312			`j dskioctl`
313			`dioser:`
314			`add $4,$5,$0`
315			`add $5,$6,$0`
316			`add $6,$7,$0`
317			`ldw $7,$29,16`
318			`j dskioser`
319
320			`;***************************************************************`
321
322			`.code`
323			`.align 4`
324
325			`; Bool saveState(MonitorState *msp)`
326			`; always return 'true' here`
327			`saveState:`
328			`stw $31,$4,0*4 ; return address`
329			`stw $29,$4,1*4 ; stack pointer`
330			`stw $16,$4,2*4 ; local variables`
331			`stw $17,$4,3*4`
332			`stw $18,$4,4*4`
333			`stw $19,$4,5*4`
334			`stw $20,$4,6*4`
335			`stw $21,$4,7*4`
336			`stw $22,$4,8*4`
337			`stw $23,$4,9*4`
338			`add $2,$0,1`
339			`jr $31`
340
341			`; load state when re-entering monitor`
342			`; this appears as if returning from saveState`
343			`; but the return value is 'false' here`
344			`loadState:`
345			`ldw $8,$0,monitorReturn`
346			`beq $8,$0,loadState ; fatal error: monitor state lost`
347			`ldw $31,$8,0*4 ; return address`
348			`ldw $29,$8,1*4 ; stack pointer`
349			`ldw $16,$8,2*4 ; local variables`
350			`ldw $17,$8,3*4`
351			`ldw $18,$8,4*4`
352			`ldw $19,$8,5*4`
353			`ldw $20,$8,6*4`
354			`ldw $21,$8,7*4`
355			`ldw $22,$8,8*4`
356			`ldw $23,$8,9*4`
357			`add $2,$0,0`
358			`jr $31`
359
360			`.bss`
361			`.align 4`
362
363			`; extern MonitorState *monitorReturn`
364			`monitorReturn:`
365			`.space 4`
366
367			`; extern UserContext userContext`
368			`userContext:`
369			`.space USER_CONTEXT_SIZE`
370
371			`;***************************************************************`
372
373			`.code`
374			`.align 4`
375
376			`; void resume(void)`
377			`; use userContext to load state`
378			`resume:`
379			`mvts $0,PSW`
380			`add $28,$0,userContext`
381			`.nosyn`
382			`ldw $8,$28,33*4 ; tlbIndex`
383			`mvts $8,TLB_INDEX`
384			`ldw $8,$28,34*4 ; tlbEntryHi`
385			`mvts $8,TLB_ENTRY_HI`
386			`ldw $8,$28,35*4 ; tlbEntryLo`
387			`mvts $8,TLB_ENTRY_LO`
388			`ldw $8,$28,36*4 ; badAddress`
389			`mvts $8,BAD_ADDRESS`
390			`ldw $8,$28,37*4 ; badAccess`
391			`mvts $8,BAD_ACCESS`
392			`;ldw $0,$28,0*4 ; registers`
393			`ldw $1,$28,1*4`
394			`ldw $2,$28,2*4`
395			`ldw $3,$28,3*4`
396			`ldw $4,$28,4*4`
397			`ldw $5,$28,5*4`
398			`ldw $6,$28,6*4`
399			`ldw $7,$28,7*4`
400			`ldw $8,$28,8*4`
401			`ldw $9,$28,9*4`
402			`ldw $10,$28,10*4`
403			`ldw $11,$28,11*4`
404			`ldw $12,$28,12*4`
405			`ldw $13,$28,13*4`
406			`ldw $14,$28,14*4`
407			`ldw $15,$28,15*4`
408			`ldw $16,$28,16*4`
409			`ldw $17,$28,17*4`
410			`ldw $18,$28,18*4`
411			`ldw $19,$28,19*4`
412			`ldw $20,$28,20*4`
413			`ldw $21,$28,21*4`
414			`ldw $22,$28,22*4`
415			`ldw $23,$28,23*4`
416			`ldw $24,$28,24*4`
417			`ldw $25,$28,25*4`
418			`ldw $26,$28,26*4`
419			`ldw $27,$28,27*4`
420			`;ldw $28,$28,28*4`
421			`ldw $29,$28,29*4`
422			`ldw $30,$28,30*4`
423			`ldw $31,$28,31*4`
424			`ldw $28,$28,32*4 ; psw`
425			`mvts $28,PSW`
426			`rfx`
427			`.syn`
428
429			`; interrupt entry`
430			`; use userContext to store state`
431			`isr:`
432			`umsr:`
433			`.nosyn`
434			`ldhi $28,userContext`
435			`or $28,$28,userContext`
436			`stw $0,$28,0*4 ; registers`
437			`stw $1,$28,1*4`
438			`stw $2,$28,2*4`
439			`stw $3,$28,3*4`
440			`stw $4,$28,4*4`
441			`stw $5,$28,5*4`
442			`stw $6,$28,6*4`
443			`stw $7,$28,7*4`
444			`stw $8,$28,8*4`
445			`stw $9,$28,9*4`
446			`stw $10,$28,10*4`
447			`stw $11,$28,11*4`
448			`stw $12,$28,12*4`
449			`stw $13,$28,13*4`
450			`stw $14,$28,14*4`
451			`stw $15,$28,15*4`
452			`stw $16,$28,16*4`
453			`stw $17,$28,17*4`
454			`stw $18,$28,18*4`
455			`stw $19,$28,19*4`
456			`stw $20,$28,20*4`
457			`stw $21,$28,21*4`
458			`stw $22,$28,22*4`
459			`stw $23,$28,23*4`
460			`stw $24,$28,24*4`
461			`stw $25,$28,25*4`
462			`stw $26,$28,26*4`
463			`stw $27,$28,27*4`
464			`stw $28,$28,28*4`
465			`stw $29,$28,29*4`
466			`stw $30,$28,30*4`
467			`stw $31,$28,31*4`
468			`mvfs $8,PSW`
469			`stw $8,$28,32*4 ; psw`
470			`mvfs $8,TLB_INDEX`
471			`stw $8,$28,33*4 ; tlbIndex`
472			`mvfs $8,TLB_ENTRY_HI`
473			`stw $8,$28,34*4 ; tlbEntryHi`
474			`mvfs $8,TLB_ENTRY_LO`
475			`stw $8,$28,35*4 ; tlbEntryLo`
476			`mvfs $8,BAD_ADDRESS`
477			`stw $8,$28,36*4 ; badAddress`
478			`mvfs $8,BAD_ACCESS`
479			`stw $8,$28,37*4 ; badAccess`
480			`.syn`
481			`j loadState`