OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [simulator/] [start.s] - Blame information for rev 258

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 189 hellwig
;
2
; start.s -- ECO32 ROM monitor startup and support routines
3
;
4
 
5
;       .set    CIO_CTL,0x00            ; set console to keyboard/display
6
        .set    CIO_CTL,0x03            ; set console to serial line 0
7
 
8
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
9
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
10
 
11
        .set    PSW,0                    ; reg # of PSW
12
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
13
        .set    V,1 << V_SHIFT
14
 
15
        .set    TLB_INDEX,1             ; reg # of TLB Index
16
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
17
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
18
        .set    TLB_ENTRIES,32          ; number of TLB entries
19
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
20
        .set    BAD_ACCESS,5            ; reg # of bad access reg
21
 
22
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
23
 
24
;***************************************************************
25
 
26
        .import _ecode
27
        .import _edata
28
        .import _ebss
29
 
30
        .import kbdinit
31
        .import kbdinchk
32
        .import kbdin
33
 
34
        .import dspinit
35
        .import dspoutchk
36
        .import dspout
37
 
38
        .import ser0init
39
        .import ser0inchk
40
        .import ser0in
41
        .import ser0outchk
42
        .import ser0out
43
 
44
        .import ser1init
45
        .import ser1inchk
46
        .import ser1in
47
        .import ser1outchk
48
        .import ser1out
49
 
50
        .import dskinitctl
51
        .import dskcapctl
52
        .import dskioctl
53
 
54
        .import dskinitser
55
        .import dskcapser
56
        .import dskioser
57
 
58
        .import main
59
 
60
        .export _bcode
61
        .export _bdata
62
        .export _bbss
63
 
64
        .export setcon
65
        .export cinchk
66
        .export cin
67
        .export coutchk
68
        .export cout
69
        .export dskcap
70
        .export dskio
71
 
72
        .export getTLB_HI
73
        .export getTLB_LO
74
        .export setTLB
75
 
76
        .export saveState
77
        .export monitorReturn
78
 
79
        .import userContext
80
        .export resume
81
 
82
;***************************************************************
83
 
84
        .code
85
_bcode:
86
 
87
        .data
88
_bdata:
89
 
90
        .bss
91
_bbss:
92
 
93
;***************************************************************
94
 
95
        .code
96
        .align  4
97
 
98
startup:
99
        j       start
100
 
101
interrupt:
102 200 hellwig
        j       debug
103 189 hellwig
 
104
userMiss:
105 200 hellwig
        j       debug
106 189 hellwig
 
107 200 hellwig
monitor:
108
        j       debug
109
 
110 189 hellwig
;***************************************************************
111
 
112
        .code
113
        .align  4
114
 
115
setcon:
116
        j       setcio
117
 
118
cinchk:
119
        j       cichk
120
 
121
cin:
122
        j       ci
123
 
124
coutchk:
125
        j       cochk
126
 
127
cout:
128
        j       co
129
 
130
dskcap:
131
        j       dcap
132
 
133
dskio:
134
        j       dio
135
 
136 200 hellwig
reserved_11:
137
        j       reserved_11
138 189 hellwig
 
139 200 hellwig
reserved_12:
140
        j       reserved_12
141 189 hellwig
 
142 200 hellwig
reserved_13:
143
        j       reserved_13
144 189 hellwig
 
145 200 hellwig
reserved_14:
146
        j       reserved_14
147 189 hellwig
 
148 200 hellwig
reserved_15:
149
        j       reserved_15
150 189 hellwig
 
151
;***************************************************************
152
 
153
        .code
154
        .align  4
155
 
156
start:
157
        ; let irq/exc vectors point to RAM
158
        add     $8,$0,V
159
        mvts    $8,PSW
160
 
161
        ; initialize TLB
162
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
163
        add     $8,$0,dmapaddr           ; by impossible virtual page number
164
        mvts    $8,TLB_ENTRY_HI
165
        add     $8,$0,$0
166
        add     $9,$0,TLB_ENTRIES
167
tlbloop:
168
        mvts    $8,TLB_INDEX
169
        tbwi
170
        add     $8,$8,1
171
        bne     $8,$9,tlbloop
172
 
173
        ; copy data segment
174
        add     $10,$0,_bdata            ; lowest dst addr to be written to
175
        add     $8,$0,_edata             ; one above the top dst addr
176
        sub     $9,$8,$10               ; $9 = size of data segment
177
        add     $9,$9,_ecode            ; data is waiting right after code
178
        j       cpytest
179
cpyloop:
180
        ldw     $11,$9,0         ; src addr in $9
181
        stw     $11,$8,0         ; dst addr in $8
182
cpytest:
183
        sub     $8,$8,4                 ; downward
184
        sub     $9,$9,4
185
        bgeu    $8,$10,cpyloop
186
 
187
        ; clear bss segment
188
        add     $8,$0,_bbss              ; start with first word of bss
189
        add     $9,$0,_ebss              ; this is one above the top
190
        j       clrtest
191
clrloop:
192
        stw     $0,$8,0                   ; dst addr in $8
193
        add     $8,$8,4                 ; upward
194
clrtest:
195
        bltu    $8,$9,clrloop
196
 
197
        ; initialize I/O
198
        add     $29,$0,stacktop          ; setup monitor stack
199
        jal     kbdinit                 ; init keyboard
200
        jal     dspinit                 ; init display
201
        jal     ser0init                ; init serial line 0
202
        jal     ser1init                ; init serial line 1
203
        jal     dskinitctl              ; init disk (controller)
204
        jal     dskinitser              ; init disk (serial line)
205
        add     $4,$0,CIO_CTL            ; set console
206
        jal     setcio
207
 
208
        ; call main
209
        jal     main                    ; enter command loop
210
 
211
        ; main should never return
212
        j       start                   ; just to be sure...
213
 
214
;***************************************************************
215
 
216
        .code
217
        .align  4
218
 
219
        ; Word getTLB_HI(int index)
220
getTLB_HI:
221
        mvts    $4,TLB_INDEX
222
        tbri
223
        mvfs    $2,TLB_ENTRY_HI
224
        jr      $31
225
 
226
        ; Word getTLB_LO(int index)
227
getTLB_LO:
228
        mvts    $4,TLB_INDEX
229
        tbri
230
        mvfs    $2,TLB_ENTRY_LO
231
        jr      $31
232
 
233
        ; void setTLB(int index, Word entryHi, Word entryLo)
234
setTLB:
235
        mvts    $4,TLB_INDEX
236
        mvts    $5,TLB_ENTRY_HI
237
        mvts    $6,TLB_ENTRY_LO
238
        tbwi
239
        jr      $31
240
 
241
;***************************************************************
242
 
243
        .data
244
        .align  4
245
 
246
cioctl:
247
        .byte   0
248
 
249
        .code
250
        .align  4
251
 
252
        ; void setcon(Byte ctl)
253
setcio:
254
        stb     $4,$0,cioctl
255
        j       $31
256
 
257
        ; int cinchk(void)
258
cichk:
259
        ldbu    $8,$0,cioctl
260
        and     $8,$8,0x01
261
        bne     $8,$0,cichk1
262
        j       kbdinchk
263
cichk1:
264
        j       ser0inchk
265
 
266
        ; char cin(void)
267
ci:
268
        ldbu    $8,$0,cioctl
269
        and     $8,$8,0x01
270
        bne     $8,$0,ci1
271
        j       kbdin
272
ci1:
273
        j       ser0in
274
 
275
        ; int coutchk(void)
276
cochk:
277
        ldbu    $8,$0,cioctl
278
        and     $8,$8,0x02
279
        bne     $8,$0,cochk1
280
        j       dspoutchk
281
cochk1:
282
        j       ser0outchk
283
 
284
        ; void cout(char c)
285
co:
286
        ldbu    $8,$0,cioctl
287
        and     $8,$8,0x02
288
        bne     $8,$0,co1
289
        j       dspout
290
co1:
291
        j       ser0out
292
 
293
;***************************************************************
294
 
295
        .code
296
        .align  4
297
 
298
        ; int dskcap(int dskno)
299
dcap:
300
        bne     $4,$0,dcapser
301
        j       dskcapctl
302
dcapser:
303
        j       dskcapser
304
 
305
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
306
dio:
307
        bne     $4,$0,dioser
308
        add     $4,$5,$0
309
        add     $5,$6,$0
310
        add     $6,$7,$0
311
        ldw     $7,$29,16
312
        j       dskioctl
313
dioser:
314
        add     $4,$5,$0
315
        add     $5,$6,$0
316
        add     $6,$7,$0
317
        ldw     $7,$29,16
318
        j       dskioser
319
 
320
;***************************************************************
321
 
322
        .code
323
        .align  4
324
 
325
        ; Bool saveState(MonitorState *msp)
326
        ; always return 'true' here
327
saveState:
328
        stw     $31,$4,0*4               ; return address
329
        stw     $29,$4,1*4              ; stack pointer
330
        stw     $16,$4,2*4              ; local variables
331
        stw     $17,$4,3*4
332
        stw     $18,$4,4*4
333
        stw     $19,$4,5*4
334
        stw     $20,$4,6*4
335
        stw     $21,$4,7*4
336
        stw     $22,$4,8*4
337
        stw     $23,$4,9*4
338
        add     $2,$0,1
339
        jr      $31
340
 
341
        ; load state when re-entering monitor
342
        ; this appears as if returning from saveState
343
        ; but the return value is 'false' here
344
loadState:
345
        ldw     $8,$0,monitorReturn
346
        beq     $8,$0,loadState          ; fatal error: monitor state lost
347
        ldw     $31,$8,0*4               ; return address
348
        ldw     $29,$8,1*4              ; stack pointer
349
        ldw     $16,$8,2*4              ; local variables
350
        ldw     $17,$8,3*4
351
        ldw     $18,$8,4*4
352
        ldw     $19,$8,5*4
353
        ldw     $20,$8,6*4
354
        ldw     $21,$8,7*4
355
        ldw     $22,$8,8*4
356
        ldw     $23,$8,9*4
357
        add     $2,$0,0
358
        jr      $31
359
 
360
        .bss
361
        .align  4
362
 
363
        ; extern MonitorState *monitorReturn
364
monitorReturn:
365
        .space  4
366
 
367
        ; extern UserContext userContext
368
userContext:
369
        .space  USER_CONTEXT_SIZE
370
 
371
;***************************************************************
372
 
373
        .code
374
        .align  4
375
 
376
        ; void resume(void)
377
        ; use userContext to load state
378
resume:
379
        mvts    $0,PSW
380 201 hellwig
        add     $24,$0,userContext
381 189 hellwig
        .nosyn
382 201 hellwig
        ldw     $8,$24,33*4             ; tlbIndex
383 189 hellwig
        mvts    $8,TLB_INDEX
384 201 hellwig
        ldw     $8,$24,34*4             ; tlbEntryHi
385 189 hellwig
        mvts    $8,TLB_ENTRY_HI
386 201 hellwig
        ldw     $8,$24,35*4             ; tlbEntryLo
387 189 hellwig
        mvts    $8,TLB_ENTRY_LO
388 201 hellwig
        ldw     $8,$24,36*4             ; badAddress
389 189 hellwig
        mvts    $8,BAD_ADDRESS
390 201 hellwig
        ldw     $8,$24,37*4             ; badAccess
391 189 hellwig
        mvts    $8,BAD_ACCESS
392 201 hellwig
        ;ldw    $0,$24,0*4              ; registers
393
        ldw     $1,$24,1*4
394
        ldw     $2,$24,2*4
395
        ldw     $3,$24,3*4
396
        ldw     $4,$24,4*4
397
        ldw     $5,$24,5*4
398
        ldw     $6,$24,6*4
399
        ldw     $7,$24,7*4
400
        ldw     $8,$24,8*4
401
        ldw     $9,$24,9*4
402
        ldw     $10,$24,10*4
403
        ldw     $11,$24,11*4
404
        ldw     $12,$24,12*4
405
        ldw     $13,$24,13*4
406
        ldw     $14,$24,14*4
407
        ldw     $15,$24,15*4
408
        ldw     $16,$24,16*4
409
        ldw     $17,$24,17*4
410
        ldw     $18,$24,18*4
411
        ldw     $19,$24,19*4
412
        ldw     $20,$24,20*4
413
        ldw     $21,$24,21*4
414
        ldw     $22,$24,22*4
415
        ldw     $23,$24,23*4
416
        ;ldw    $24,$24,24*4
417
        ldw     $25,$24,25*4
418
        ldw     $26,$24,26*4
419
        ldw     $27,$24,27*4
420
        ldw     $28,$24,28*4
421
        ldw     $29,$24,29*4
422
        ldw     $30,$24,30*4
423
        ldw     $31,$24,31*4
424
        ldw     $24,$24,32*4            ; psw
425
        mvts    $24,PSW
426 189 hellwig
        rfx
427
        .syn
428
 
429 200 hellwig
        ; debug entry
430 189 hellwig
        ; use userContext to store state
431 200 hellwig
debug:
432 189 hellwig
        .nosyn
433 201 hellwig
        ldhi    $24,userContext
434
        or      $24,$24,userContext
435
        stw     $0,$24,0*4                ; registers
436
        stw     $1,$24,1*4
437
        stw     $2,$24,2*4
438
        stw     $3,$24,3*4
439
        stw     $4,$24,4*4
440
        stw     $5,$24,5*4
441
        stw     $6,$24,6*4
442
        stw     $7,$24,7*4
443
        stw     $8,$24,8*4
444
        stw     $9,$24,9*4
445
        stw     $10,$24,10*4
446
        stw     $11,$24,11*4
447
        stw     $12,$24,12*4
448
        stw     $13,$24,13*4
449
        stw     $14,$24,14*4
450
        stw     $15,$24,15*4
451
        stw     $16,$24,16*4
452
        stw     $17,$24,17*4
453
        stw     $18,$24,18*4
454
        stw     $19,$24,19*4
455
        stw     $20,$24,20*4
456
        stw     $21,$24,21*4
457
        stw     $22,$24,22*4
458
        stw     $23,$24,23*4
459
        stw     $24,$24,24*4
460
        stw     $25,$24,25*4
461
        stw     $26,$24,26*4
462
        stw     $27,$24,27*4
463
        stw     $28,$24,28*4
464
        stw     $29,$24,29*4
465
        stw     $30,$24,30*4
466
        stw     $31,$24,31*4
467 189 hellwig
        mvfs    $8,PSW
468 201 hellwig
        stw     $8,$24,32*4             ; psw
469 189 hellwig
        mvfs    $8,TLB_INDEX
470 201 hellwig
        stw     $8,$24,33*4             ; tlbIndex
471 189 hellwig
        mvfs    $8,TLB_ENTRY_HI
472 201 hellwig
        stw     $8,$24,34*4             ; tlbEntryHi
473 189 hellwig
        mvfs    $8,TLB_ENTRY_LO
474 201 hellwig
        stw     $8,$24,35*4             ; tlbEntryLo
475 189 hellwig
        mvfs    $8,BAD_ADDRESS
476 201 hellwig
        stw     $8,$24,36*4             ; badAddress
477 189 hellwig
        mvfs    $8,BAD_ACCESS
478 201 hellwig
        stw     $8,$24,37*4             ; badAccess
479 189 hellwig
        .syn
480
        j       loadState

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.