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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 117

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Line No. Rev Author Line
1 16 hellwig
;
2
; start.s -- ECO32 ROM monitor startup and support routines
3
;
4
 
5
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
6 55 hellwig
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
7 16 hellwig
 
8
        .set    PSW,0                    ; reg # of PSW
9 55 hellwig
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
10
        .set    V,1 << V_SHIFT
11
 
12 16 hellwig
        .set    TLB_INDEX,1             ; reg # of TLB Index
13
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
14
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
15
        .set    TLB_ENTRIES,32          ; number of TLB entries
16 84 hellwig
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
17 16 hellwig
 
18 84 hellwig
        .set    USER_CONTEXT_SIZE,37*4  ; size of user context
19 16 hellwig
 
20
;***************************************************************
21
 
22
        .import _ecode
23
        .import _edata
24
        .import _ebss
25
 
26
        .import kbdinit
27
        .import kbdinchk
28
        .import kbdin
29
 
30
        .import dspinit
31
        .import dspoutchk
32
        .import dspout
33
 
34
        .import serinit
35
        .import ser0inchk
36
        .import ser0in
37
        .import ser0outchk
38
        .import ser0out
39
 
40
        .import sctcapctl
41
        .import sctioctl
42
        .import sctcapser
43
        .import sctioser
44
 
45
        .import main
46
 
47
        .export _bcode
48
        .export _bdata
49
        .export _bbss
50
 
51
        .export cinchk
52
        .export cin
53
        .export coutchk
54
        .export cout
55
        .export sinchk
56
        .export sin
57
        .export soutchk
58
        .export sout
59
        .export dskcap
60
        .export dskio
61
 
62 55 hellwig
        .export setISR
63
        .export setUMSR
64
        .export isrPtr
65
        .export umsrPtr
66
 
67 16 hellwig
        .export getTLB_HI
68
        .export getTLB_LO
69
        .export setTLB
70
 
71
        .export saveState
72
        .export monitorReturn
73
 
74
        .import userContext
75
        .export resume
76
 
77
;***************************************************************
78
 
79
        .code
80
_bcode:
81
 
82
        .data
83
_bdata:
84
 
85
        .bss
86
_bbss:
87
 
88
;***************************************************************
89
 
90
        .code
91
        .align  4
92
 
93
reset:
94
        j       start
95
 
96
interrupt:
97
        j       isr
98
 
99
userMiss:
100
        j       umsr
101
 
102
;***************************************************************
103
 
104
        .code
105
        .align  4
106
 
107
cinchk:
108 65 hellwig
;       j       kbdinchk
109
        j       ser0inchk
110 16 hellwig
 
111
cin:
112 65 hellwig
;       j       kbdin
113
        j       ser0in
114 16 hellwig
 
115
coutchk:
116 65 hellwig
;       j       dspoutchk
117
        j       ser0outchk
118 16 hellwig
 
119
cout:
120 65 hellwig
;       j       dspout
121
        j       ser0out
122 16 hellwig
 
123
sinchk:
124
        j       ser0inchk
125
 
126
sin:
127
        j       ser0in
128
 
129
soutchk:
130
        j       ser0outchk
131
 
132
sout:
133
        j       ser0out
134
 
135
dskcap:
136
        j       dcap
137
 
138
dskio:
139
        j       dio
140
 
141 55 hellwig
reserved1:
142
        j       reserved1
143
 
144
reserved2:
145
        j       reserved2
146
 
147
reserved3:
148
        j       reserved3
149
 
150
setISR:
151
        j       setISR1
152
 
153
setUMSR:
154
        j       setUMSR1
155
 
156 16 hellwig
;***************************************************************
157
 
158
        .code
159
        .align  4
160
 
161
start:
162 55 hellwig
        ; let irq/exc vectors point to RAM
163
        add     $8,$0,V
164
        mvts    $8,PSW
165 16 hellwig
 
166
        ; initialize TLB
167
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
168
        add     $8,$0,dmapaddr           ; by impossible virtual page number
169
        add     $9,$0,$0
170
        add     $10,$0,TLB_ENTRIES
171
tlbloop:
172
        mvts    $8,TLB_ENTRY_HI
173
        mvts    $9,TLB_INDEX
174
        tbwi
175
        add     $8,$8,0x1000            ; all entries must be different
176
        add     $9,$9,1
177
        bne     $9,$10,tlbloop
178
 
179
        ; copy data segment
180
        add     $10,$0,_bdata            ; lowest dst addr to be written to
181
        add     $8,$0,_edata             ; one above the top dst addr
182
        sub     $9,$8,$10               ; $9 = size of data segment
183
        add     $9,$9,_ecode            ; data is waiting right after code
184
        j       cpytest
185
cpyloop:
186
        ldw     $11,$9,0         ; src addr in $9
187
        stw     $11,$8,0         ; dst addr in $8
188
cpytest:
189
        sub     $8,$8,4                 ; downward
190
        sub     $9,$9,4
191
        bgeu    $8,$10,cpyloop
192
 
193
        ; clear bss segment
194
        add     $8,$0,_bbss              ; start with first word of bss
195
        add     $9,$0,_ebss              ; this is one above the top
196
        j       clrtest
197
clrloop:
198
        stw     $0,$8,0                   ; dst addr in $8
199
        add     $8,$8,4                 ; upward
200
clrtest:
201
        bltu    $8,$9,clrloop
202
 
203
        ; now do some useful work
204
        add     $29,$0,stacktop          ; setup monitor stack
205 55 hellwig
        jal     dspinit                 ; init display
206
        jal     kbdinit                 ; init keyboard
207 16 hellwig
        jal     serinit                 ; init serial interface
208
        jal     main                    ; enter command loop
209
 
210
        ; main should never return
211
        j       start                   ; just to be sure...
212
 
213
;***************************************************************
214
 
215 55 hellwig
        .code
216
        .align  4
217
 
218 16 hellwig
        ; Word getTLB_HI(int index)
219
getTLB_HI:
220
        mvts    $4,TLB_INDEX
221
        tbri
222
        mvfs    $2,TLB_ENTRY_HI
223
        jr      $31
224
 
225
        ; Word getTLB_LO(int index)
226
getTLB_LO:
227
        mvts    $4,TLB_INDEX
228
        tbri
229
        mvfs    $2,TLB_ENTRY_LO
230
        jr      $31
231
 
232
        ; void setTLB(int index, Word entryHi, Word entryLo)
233
setTLB:
234
        mvts    $4,TLB_INDEX
235
        mvts    $5,TLB_ENTRY_HI
236
        mvts    $6,TLB_ENTRY_LO
237
        tbwi
238
        jr      $31
239
 
240
;***************************************************************
241
 
242 55 hellwig
        .code
243
        .align  4
244
 
245 16 hellwig
        ; int dskcap(int dskno)
246
dcap:
247
        bne     $4,$0,dcapser
248
        j       sctcapctl
249
dcapser:
250
        j       sctcapser
251
 
252
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
253
dio:
254
        bne     $4,$0,dioser
255
        add     $4,$5,$0
256
        add     $5,$6,$0
257
        add     $6,$7,$0
258
        ldw     $7,$29,16
259
        j       sctioctl
260
dioser:
261
        add     $4,$5,$0
262
        add     $5,$6,$0
263
        add     $6,$7,$0
264
        ldw     $7,$29,16
265
        j       sctioser
266
 
267
;***************************************************************
268
 
269
        .code
270
        .align  4
271
 
272 55 hellwig
        ; void setISR(Word ptr)
273
setISR1:
274
        stw     $4,$0,isrPtr
275
        jr      $31
276
 
277
        ; void setUMSR(Word ptr)
278
setUMSR1:
279
        stw     $4,$0,umsrPtr
280
        jr      $31
281
 
282
        .data
283
        .align  4
284
 
285
isrPtr:
286
        .word   0
287
 
288
umsrPtr:
289
        .word   0
290
 
291
;***************************************************************
292
 
293
        .code
294
        .align  4
295
 
296 16 hellwig
        ; Bool saveState(MonitorState *msp)
297
        ; always return 'true' here
298
saveState:
299
        stw     $31,$4,0*4               ; return address
300
        stw     $29,$4,1*4              ; stack pointer
301
        stw     $16,$4,2*4              ; local variables
302
        stw     $17,$4,3*4
303
        stw     $18,$4,4*4
304
        stw     $19,$4,5*4
305
        stw     $20,$4,6*4
306
        stw     $21,$4,7*4
307
        stw     $22,$4,8*4
308
        stw     $23,$4,9*4
309
        add     $2,$0,1
310
        jr      $31
311
 
312
        ; load state when re-entering monitor
313
        ; this appears as if returning from saveState
314
        ; but the return value is 'false' here
315
loadState:
316
        ldw     $8,$0,monitorReturn
317
        beq     $8,$0,loadState          ; fatal error: monitor state lost
318
        ldw     $31,$8,0*4               ; return address
319
        ldw     $29,$8,1*4              ; stack pointer
320
        ldw     $16,$8,2*4              ; local variables
321
        ldw     $17,$8,3*4
322
        ldw     $18,$8,4*4
323
        ldw     $19,$8,5*4
324
        ldw     $20,$8,6*4
325
        ldw     $21,$8,7*4
326
        ldw     $22,$8,8*4
327
        ldw     $23,$8,9*4
328
        add     $2,$0,0
329
        jr      $31
330
 
331
        .bss
332
        .align  4
333
 
334
        ; extern MonitorState *monitorReturn
335
monitorReturn:
336
        .space  4
337
 
338
        ; extern UserContext userContext
339
userContext:
340
        .space  USER_CONTEXT_SIZE
341
 
342
;***************************************************************
343
 
344
        .code
345
        .align  4
346
 
347
        ; void resume(void)
348
        ; use userContext to load state
349
resume:
350
        mvts    $0,PSW
351
        add     $28,$0,userContext
352
        .nosyn
353
        ldw     $8,$28,33*4             ; tlbIndex
354
        mvts    $8,TLB_INDEX
355 55 hellwig
        ldw     $8,$28,34*4             ; tlbEntryHi
356 16 hellwig
        mvts    $8,TLB_ENTRY_HI
357
        ldw     $8,$28,35*4             ; tlbEntryLo
358
        mvts    $8,TLB_ENTRY_LO
359 84 hellwig
        ldw     $8,$28,36*4             ; badAddress
360
        mvts    $8,BAD_ADDRESS
361 16 hellwig
        ;ldw    $0,$28,0*4              ; registers
362
        ldw     $1,$28,1*4
363
        ldw     $2,$28,2*4
364
        ldw     $3,$28,3*4
365
        ldw     $4,$28,4*4
366
        ldw     $5,$28,5*4
367
        ldw     $6,$28,6*4
368
        ldw     $7,$28,7*4
369
        ldw     $8,$28,8*4
370
        ldw     $9,$28,9*4
371
        ldw     $10,$28,10*4
372
        ldw     $11,$28,11*4
373
        ldw     $12,$28,12*4
374
        ldw     $13,$28,13*4
375
        ldw     $14,$28,14*4
376
        ldw     $15,$28,15*4
377
        ldw     $16,$28,16*4
378
        ldw     $17,$28,17*4
379
        ldw     $18,$28,18*4
380
        ldw     $19,$28,19*4
381
        ldw     $20,$28,20*4
382
        ldw     $21,$28,21*4
383
        ldw     $22,$28,22*4
384
        ldw     $23,$28,23*4
385
        ldw     $24,$28,24*4
386
        ldw     $25,$28,25*4
387
        ldw     $26,$28,26*4
388
        ldw     $27,$28,27*4
389
        ;ldw    $28,$28,28*4
390
        ldw     $29,$28,29*4
391
        ldw     $30,$28,30*4
392
        ldw     $31,$28,31*4
393
        ldw     $28,$28,32*4            ; psw
394
        mvts    $28,PSW
395
        rfx
396
        .syn
397
 
398
        ; interrupt entry
399
        ; use userContext to store state
400
isr:
401
umsr:
402
        .nosyn
403
        ldhi    $28,userContext
404
        or      $28,$28,userContext
405
        stw     $0,$28,0*4                ; registers
406
        stw     $1,$28,1*4
407
        stw     $2,$28,2*4
408
        stw     $3,$28,3*4
409
        stw     $4,$28,4*4
410
        stw     $5,$28,5*4
411
        stw     $6,$28,6*4
412
        stw     $7,$28,7*4
413
        stw     $8,$28,8*4
414
        stw     $9,$28,9*4
415
        stw     $10,$28,10*4
416
        stw     $11,$28,11*4
417
        stw     $12,$28,12*4
418
        stw     $13,$28,13*4
419
        stw     $14,$28,14*4
420
        stw     $15,$28,15*4
421
        stw     $16,$28,16*4
422
        stw     $17,$28,17*4
423
        stw     $18,$28,18*4
424
        stw     $19,$28,19*4
425
        stw     $20,$28,20*4
426
        stw     $21,$28,21*4
427
        stw     $22,$28,22*4
428
        stw     $23,$28,23*4
429
        stw     $24,$28,24*4
430
        stw     $25,$28,25*4
431
        stw     $26,$28,26*4
432
        stw     $27,$28,27*4
433
        stw     $28,$28,28*4
434
        stw     $29,$28,29*4
435
        stw     $30,$28,30*4
436
        stw     $31,$28,31*4
437
        mvfs    $8,PSW
438
        stw     $8,$28,32*4             ; psw
439
        mvfs    $8,TLB_INDEX
440
        stw     $8,$28,33*4             ; tlbIndex
441
        mvfs    $8,TLB_ENTRY_HI
442
        stw     $8,$28,34*4             ; tlbEntryHi
443
        mvfs    $8,TLB_ENTRY_LO
444
        stw     $8,$28,35*4             ; tlbEntryLo
445 84 hellwig
        mvfs    $8,BAD_ADDRESS
446
        stw     $8,$28,36*4             ; badAddress
447 16 hellwig
        .syn
448
        j       loadState

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