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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 180

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import serinit
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import sctcapctl
        .import sctioctl
        .import sctcapser
        .import sctioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export sinchk
        .export sin
        .export soutchk
        .export sout
        .export dskcap
        .export dskio
 
        .export setISR
        .export setUMSR
        .export isrPtr
        .export umsrPtr
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
cinchk:
;       j       kbdinchk
        j       ser0inchk
 
cin:
;       j       kbdin
        j       ser0in
 
coutchk:
;       j       dspoutchk
        j       ser0outchk
 
cout:
;       j       dspout
        j       ser0out
 
sinchk:
        j       ser0inchk
 
sin:
        j       ser0in
 
soutchk:
        j       ser0outchk
 
sout:
        j       ser0out
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved1:
        j       reserved1
 
reserved2:
        j       reserved2
 
reserved3:
        j       reserved3
 
setISR:
        j       setISR1
 
setUMSR:
        j       setUMSR1
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        add     $9,$0,$0
        add     $10,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_ENTRY_HI
        mvts    $9,TLB_INDEX
        tbwi
        add     $8,$8,0x1000            ; all entries must be different
        add     $9,$9,1
        bne     $9,$10,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     dspinit                 ; init display
        jal     kbdinit                 ; init keyboard
        jal     serinit                 ; init serial interface
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       sctcapctl
dcapser:
        j       sctcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; void setISR(Word ptr)
setISR1:
        stw     $4,$0,isrPtr
        jr      $31
 
        ; void setUMSR(Word ptr)
setUMSR1:
        stw     $4,$0,umsrPtr
        jr      $31
 
        .data
        .align  4
 
isrPtr:
        .word   0
 
umsrPtr:
        .word   0
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$28,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$28,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$28,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$28,37*4             ; badAccess
        .syn
        j       loadState

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6	55	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
7	16	hellwig
8			`.set PSW,0 ; reg # of PSW`
9	55	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
10			`.set V,1 << V_SHIFT`
11
12	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
13			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
14			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
15			`.set TLB_ENTRIES,32 ; number of TLB entries`
16	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
17	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
18	16	hellwig
19	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
20	16	hellwig
21			`;***************************************************************`
22
23			`.import _ecode`
24			`.import _edata`
25			`.import _ebss`
26
27			`.import kbdinit`
28			`.import kbdinchk`
29			`.import kbdin`
30
31			`.import dspinit`
32			`.import dspoutchk`
33			`.import dspout`
34
35			`.import serinit`
36			`.import ser0inchk`
37			`.import ser0in`
38			`.import ser0outchk`
39			`.import ser0out`
40
41			`.import sctcapctl`
42			`.import sctioctl`
43			`.import sctcapser`
44			`.import sctioser`
45
46			`.import main`
47
48			`.export _bcode`
49			`.export _bdata`
50			`.export _bbss`
51
52			`.export cinchk`
53			`.export cin`
54			`.export coutchk`
55			`.export cout`
56			`.export sinchk`
57			`.export sin`
58			`.export soutchk`
59			`.export sout`
60			`.export dskcap`
61			`.export dskio`
62
63	55	hellwig	`.export setISR`
64			`.export setUMSR`
65			`.export isrPtr`
66			`.export umsrPtr`
67
68	16	hellwig	`.export getTLB_HI`
69			`.export getTLB_LO`
70			`.export setTLB`
71
72			`.export saveState`
73			`.export monitorReturn`
74
75			`.import userContext`
76			`.export resume`
77
78			`;***************************************************************`
79
80			`.code`
81			`_bcode:`
82
83			`.data`
84			`_bdata:`
85
86			`.bss`
87			`_bbss:`
88
89			`;***************************************************************`
90
91			`.code`
92			`.align 4`
93
94			`reset:`
95			`j start`
96
97			`interrupt:`
98			`j isr`
99
100			`userMiss:`
101			`j umsr`
102
103			`;***************************************************************`
104
105			`.code`
106			`.align 4`
107
108			`cinchk:`
109	65	hellwig	`; j kbdinchk`
110			`j ser0inchk`
111	16	hellwig
112			`cin:`
113	65	hellwig	`; j kbdin`
114			`j ser0in`
115	16	hellwig
116			`coutchk:`
117	65	hellwig	`; j dspoutchk`
118			`j ser0outchk`
119	16	hellwig
120			`cout:`
121	65	hellwig	`; j dspout`
122			`j ser0out`
123	16	hellwig
124			`sinchk:`
125			`j ser0inchk`
126
127			`sin:`
128			`j ser0in`
129
130			`soutchk:`
131			`j ser0outchk`
132
133			`sout:`
134			`j ser0out`
135
136			`dskcap:`
137			`j dcap`
138
139			`dskio:`
140			`j dio`
141
142	55	hellwig	`reserved1:`
143			`j reserved1`
144
145			`reserved2:`
146			`j reserved2`
147
148			`reserved3:`
149			`j reserved3`
150
151			`setISR:`
152			`j setISR1`
153
154			`setUMSR:`
155			`j setUMSR1`
156
157	16	hellwig	`;***************************************************************`
158
159			`.code`
160			`.align 4`
161
162			`start:`
163	55	hellwig	`; let irq/exc vectors point to RAM`
164			`add $8,$0,V`
165			`mvts $8,PSW`
166	16	hellwig
167			`; initialize TLB`
168			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
169			`add $8,$0,dmapaddr ; by impossible virtual page number`
170			`add $9,$0,$0`
171			`add $10,$0,TLB_ENTRIES`
172			`tlbloop:`
173			`mvts $8,TLB_ENTRY_HI`
174			`mvts $9,TLB_INDEX`
175			`tbwi`
176			`add $8,$8,0x1000 ; all entries must be different`
177			`add $9,$9,1`
178			`bne $9,$10,tlbloop`
179
180			`; copy data segment`
181			`add $10,$0,_bdata ; lowest dst addr to be written to`
182			`add $8,$0,_edata ; one above the top dst addr`
183			`sub $9,$8,$10 ; $9 = size of data segment`
184			`add $9,$9,_ecode ; data is waiting right after code`
185			`j cpytest`
186			`cpyloop:`
187			`ldw $11,$9,0 ; src addr in $9`
188			`stw $11,$8,0 ; dst addr in $8`
189			`cpytest:`
190			`sub $8,$8,4 ; downward`
191			`sub $9,$9,4`
192			`bgeu $8,$10,cpyloop`
193
194			`; clear bss segment`
195			`add $8,$0,_bbss ; start with first word of bss`
196			`add $9,$0,_ebss ; this is one above the top`
197			`j clrtest`
198			`clrloop:`
199			`stw $0,$8,0 ; dst addr in $8`
200			`add $8,$8,4 ; upward`
201			`clrtest:`
202			`bltu $8,$9,clrloop`
203
204			`; now do some useful work`
205			`add $29,$0,stacktop ; setup monitor stack`
206	55	hellwig	`jal dspinit ; init display`
207			`jal kbdinit ; init keyboard`
208	16	hellwig	`jal serinit ; init serial interface`
209			`jal main ; enter command loop`
210
211			`; main should never return`
212			`j start ; just to be sure...`
213
214			`;***************************************************************`
215
216	55	hellwig	`.code`
217			`.align 4`
218
219	16	hellwig	`; Word getTLB_HI(int index)`
220			`getTLB_HI:`
221			`mvts $4,TLB_INDEX`
222			`tbri`
223			`mvfs $2,TLB_ENTRY_HI`
224			`jr $31`
225
226			`; Word getTLB_LO(int index)`
227			`getTLB_LO:`
228			`mvts $4,TLB_INDEX`
229			`tbri`
230			`mvfs $2,TLB_ENTRY_LO`
231			`jr $31`
232
233			`; void setTLB(int index, Word entryHi, Word entryLo)`
234			`setTLB:`
235			`mvts $4,TLB_INDEX`
236			`mvts $5,TLB_ENTRY_HI`
237			`mvts $6,TLB_ENTRY_LO`
238			`tbwi`
239			`jr $31`
240
241			`;***************************************************************`
242
243	55	hellwig	`.code`
244			`.align 4`
245
246	16	hellwig	`; int dskcap(int dskno)`
247			`dcap:`
248			`bne $4,$0,dcapser`
249			`j sctcapctl`
250			`dcapser:`
251			`j sctcapser`
252
253			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
254			`dio:`
255			`bne $4,$0,dioser`
256			`add $4,$5,$0`
257			`add $5,$6,$0`
258			`add $6,$7,$0`
259			`ldw $7,$29,16`
260			`j sctioctl`
261			`dioser:`
262			`add $4,$5,$0`
263			`add $5,$6,$0`
264			`add $6,$7,$0`
265			`ldw $7,$29,16`
266			`j sctioser`
267
268			`;***************************************************************`
269
270			`.code`
271			`.align 4`
272
273	55	hellwig	`; void setISR(Word ptr)`
274			`setISR1:`
275			`stw $4,$0,isrPtr`
276			`jr $31`
277
278			`; void setUMSR(Word ptr)`
279			`setUMSR1:`
280			`stw $4,$0,umsrPtr`
281			`jr $31`
282
283			`.data`
284			`.align 4`
285
286			`isrPtr:`
287			`.word 0`
288
289			`umsrPtr:`
290			`.word 0`
291
292			`;***************************************************************`
293
294			`.code`
295			`.align 4`
296
297	16	hellwig	`; Bool saveState(MonitorState *msp)`
298			`; always return 'true' here`
299			`saveState:`
300			`stw $31,$4,0*4 ; return address`
301			`stw $29,$4,1*4 ; stack pointer`
302			`stw $16,$4,2*4 ; local variables`
303			`stw $17,$4,3*4`
304			`stw $18,$4,4*4`
305			`stw $19,$4,5*4`
306			`stw $20,$4,6*4`
307			`stw $21,$4,7*4`
308			`stw $22,$4,8*4`
309			`stw $23,$4,9*4`
310			`add $2,$0,1`
311			`jr $31`
312
313			`; load state when re-entering monitor`
314			`; this appears as if returning from saveState`
315			`; but the return value is 'false' here`
316			`loadState:`
317			`ldw $8,$0,monitorReturn`
318			`beq $8,$0,loadState ; fatal error: monitor state lost`
319			`ldw $31,$8,0*4 ; return address`
320			`ldw $29,$8,1*4 ; stack pointer`
321			`ldw $16,$8,2*4 ; local variables`
322			`ldw $17,$8,3*4`
323			`ldw $18,$8,4*4`
324			`ldw $19,$8,5*4`
325			`ldw $20,$8,6*4`
326			`ldw $21,$8,7*4`
327			`ldw $22,$8,8*4`
328			`ldw $23,$8,9*4`
329			`add $2,$0,0`
330			`jr $31`
331
332			`.bss`
333			`.align 4`
334
335			`; extern MonitorState *monitorReturn`
336			`monitorReturn:`
337			`.space 4`
338
339			`; extern UserContext userContext`
340			`userContext:`
341			`.space USER_CONTEXT_SIZE`
342
343			`;***************************************************************`
344
345			`.code`
346			`.align 4`
347
348			`; void resume(void)`
349			`; use userContext to load state`
350			`resume:`
351			`mvts $0,PSW`
352			`add $28,$0,userContext`
353			`.nosyn`
354			`ldw $8,$28,33*4 ; tlbIndex`
355			`mvts $8,TLB_INDEX`
356	55	hellwig	`ldw $8,$28,34*4 ; tlbEntryHi`
357	16	hellwig	`mvts $8,TLB_ENTRY_HI`
358			`ldw $8,$28,35*4 ; tlbEntryLo`
359			`mvts $8,TLB_ENTRY_LO`
360	84	hellwig	`ldw $8,$28,36*4 ; badAddress`
361			`mvts $8,BAD_ADDRESS`
362	180	hellwig	`ldw $8,$28,37*4 ; badAccess`
363			`mvts $8,BAD_ACCESS`
364	16	hellwig	`;ldw $0,$28,0*4 ; registers`
365			`ldw $1,$28,1*4`
366			`ldw $2,$28,2*4`
367			`ldw $3,$28,3*4`
368			`ldw $4,$28,4*4`
369			`ldw $5,$28,5*4`
370			`ldw $6,$28,6*4`
371			`ldw $7,$28,7*4`
372			`ldw $8,$28,8*4`
373			`ldw $9,$28,9*4`
374			`ldw $10,$28,10*4`
375			`ldw $11,$28,11*4`
376			`ldw $12,$28,12*4`
377			`ldw $13,$28,13*4`
378			`ldw $14,$28,14*4`
379			`ldw $15,$28,15*4`
380			`ldw $16,$28,16*4`
381			`ldw $17,$28,17*4`
382			`ldw $18,$28,18*4`
383			`ldw $19,$28,19*4`
384			`ldw $20,$28,20*4`
385			`ldw $21,$28,21*4`
386			`ldw $22,$28,22*4`
387			`ldw $23,$28,23*4`
388			`ldw $24,$28,24*4`
389			`ldw $25,$28,25*4`
390			`ldw $26,$28,26*4`
391			`ldw $27,$28,27*4`
392			`;ldw $28,$28,28*4`
393			`ldw $29,$28,29*4`
394			`ldw $30,$28,30*4`
395			`ldw $31,$28,31*4`
396			`ldw $28,$28,32*4 ; psw`
397			`mvts $28,PSW`
398			`rfx`
399			`.syn`
400
401			`; interrupt entry`
402			`; use userContext to store state`
403			`isr:`
404			`umsr:`
405			`.nosyn`
406			`ldhi $28,userContext`
407			`or $28,$28,userContext`
408			`stw $0,$28,0*4 ; registers`
409			`stw $1,$28,1*4`
410			`stw $2,$28,2*4`
411			`stw $3,$28,3*4`
412			`stw $4,$28,4*4`
413			`stw $5,$28,5*4`
414			`stw $6,$28,6*4`
415			`stw $7,$28,7*4`
416			`stw $8,$28,8*4`
417			`stw $9,$28,9*4`
418			`stw $10,$28,10*4`
419			`stw $11,$28,11*4`
420			`stw $12,$28,12*4`
421			`stw $13,$28,13*4`
422			`stw $14,$28,14*4`
423			`stw $15,$28,15*4`
424			`stw $16,$28,16*4`
425			`stw $17,$28,17*4`
426			`stw $18,$28,18*4`
427			`stw $19,$28,19*4`
428			`stw $20,$28,20*4`
429			`stw $21,$28,21*4`
430			`stw $22,$28,22*4`
431			`stw $23,$28,23*4`
432			`stw $24,$28,24*4`
433			`stw $25,$28,25*4`
434			`stw $26,$28,26*4`
435			`stw $27,$28,27*4`
436			`stw $28,$28,28*4`
437			`stw $29,$28,29*4`
438			`stw $30,$28,30*4`
439			`stw $31,$28,31*4`
440			`mvfs $8,PSW`
441			`stw $8,$28,32*4 ; psw`
442			`mvfs $8,TLB_INDEX`
443			`stw $8,$28,33*4 ; tlbIndex`
444			`mvfs $8,TLB_ENTRY_HI`
445			`stw $8,$28,34*4 ; tlbEntryHi`
446			`mvfs $8,TLB_ENTRY_LO`
447			`stw $8,$28,35*4 ; tlbEntryLo`
448	84	hellwig	`mvfs $8,BAD_ADDRESS`
449			`stw $8,$28,36*4 ; badAddress`
450	180	hellwig	`mvfs $8,BAD_ACCESS`
451			`stw $8,$28,37*4 ; badAccess`
452	16	hellwig	`.syn`
453			`j loadState`

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