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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 182

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import ser0init
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import ser1init
        .import ser1inchk
        .import ser1in
        .import ser1outchk
        .import ser1out
 
        .import dskinit
        .import dskcapctl
        .import dskioctl
        .import dskcapser
        .import dskioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export sinchk
        .export sin
        .export soutchk
        .export sout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
cinchk:
;       j       kbdinchk
        j       ser0inchk
 
cin:
;       j       kbdin
        j       ser0in
 
coutchk:
;       j       dspoutchk
        j       ser0outchk
 
cout:
;       j       dspout
        j       ser0out
 
sinchk:
        j       ser0inchk
 
sin:
        j       ser0in
 
soutchk:
        j       ser0outchk
 
sout:
        j       ser0out
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved1:
        j       reserved1
 
reserved2:
        j       reserved2
 
reserved3:
        j       reserved3
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        mvts    $8,TLB_ENTRY_HI
        add     $8,$0,$0
        add     $9,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_INDEX
        tbwi
        add     $8,$8,1
        bne     $8,$9,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     dspinit                 ; init display
        jal     kbdinit                 ; init keyboard
        jal     ser0init                ; init serial line 0
        jal     ser1init                ; init serial line 1
        jal     dskinit                 ; init disk
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       dskcapctl
dcapser:
        j       dskcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$28,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$28,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$28,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$28,37*4             ; badAccess
        .syn
        j       loadState

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6	55	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
7	16	hellwig
8			`.set PSW,0 ; reg # of PSW`
9	55	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
10			`.set V,1 << V_SHIFT`
11
12	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
13			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
14			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
15			`.set TLB_ENTRIES,32 ; number of TLB entries`
16	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
17	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
18	16	hellwig
19	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
20	16	hellwig
21			`;***************************************************************`
22
23			`.import _ecode`
24			`.import _edata`
25			`.import _ebss`
26
27	182	hellwig	`.import dspinit`
28			`.import dspoutchk`
29			`.import dspout`
30
31	16	hellwig	`.import kbdinit`
32			`.import kbdinchk`
33			`.import kbdin`
34
35	182	hellwig	`.import ser0init`
36	16	hellwig	`.import ser0inchk`
37			`.import ser0in`
38			`.import ser0outchk`
39			`.import ser0out`
40
41	182	hellwig	`.import ser1init`
42			`.import ser1inchk`
43			`.import ser1in`
44			`.import ser1outchk`
45			`.import ser1out`
46	16	hellwig
47	182	hellwig	`.import dskinit`
48			`.import dskcapctl`
49			`.import dskioctl`
50			`.import dskcapser`
51			`.import dskioser`
52
53	16	hellwig	`.import main`
54
55			`.export _bcode`
56			`.export _bdata`
57			`.export _bbss`
58
59			`.export cinchk`
60			`.export cin`
61			`.export coutchk`
62			`.export cout`
63			`.export sinchk`
64			`.export sin`
65			`.export soutchk`
66			`.export sout`
67			`.export dskcap`
68			`.export dskio`
69
70			`.export getTLB_HI`
71			`.export getTLB_LO`
72			`.export setTLB`
73
74			`.export saveState`
75			`.export monitorReturn`
76
77			`.import userContext`
78			`.export resume`
79
80			`;***************************************************************`
81
82			`.code`
83			`_bcode:`
84
85			`.data`
86			`_bdata:`
87
88			`.bss`
89			`_bbss:`
90
91			`;***************************************************************`
92
93			`.code`
94			`.align 4`
95
96			`reset:`
97			`j start`
98
99			`interrupt:`
100			`j isr`
101
102			`userMiss:`
103			`j umsr`
104
105			`;***************************************************************`
106
107			`.code`
108			`.align 4`
109
110			`cinchk:`
111	65	hellwig	`; j kbdinchk`
112			`j ser0inchk`
113	16	hellwig
114			`cin:`
115	65	hellwig	`; j kbdin`
116			`j ser0in`
117	16	hellwig
118			`coutchk:`
119	65	hellwig	`; j dspoutchk`
120			`j ser0outchk`
121	16	hellwig
122			`cout:`
123	65	hellwig	`; j dspout`
124			`j ser0out`
125	16	hellwig
126			`sinchk:`
127			`j ser0inchk`
128
129			`sin:`
130			`j ser0in`
131
132			`soutchk:`
133			`j ser0outchk`
134
135			`sout:`
136			`j ser0out`
137
138			`dskcap:`
139			`j dcap`
140
141			`dskio:`
142			`j dio`
143
144	55	hellwig	`reserved1:`
145			`j reserved1`
146
147			`reserved2:`
148			`j reserved2`
149
150			`reserved3:`
151			`j reserved3`
152
153	16	hellwig	`;***************************************************************`
154
155			`.code`
156			`.align 4`
157
158			`start:`
159	55	hellwig	`; let irq/exc vectors point to RAM`
160			`add $8,$0,V`
161			`mvts $8,PSW`
162	16	hellwig
163			`; initialize TLB`
164			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
165			`add $8,$0,dmapaddr ; by impossible virtual page number`
166	182	hellwig	`mvts $8,TLB_ENTRY_HI`
167			`add $8,$0,$0`
168			`add $9,$0,TLB_ENTRIES`
169	16	hellwig	`tlbloop:`
170	182	hellwig	`mvts $8,TLB_INDEX`
171	16	hellwig	`tbwi`
172	182	hellwig	`add $8,$8,1`
173			`bne $8,$9,tlbloop`
174	16	hellwig
175			`; copy data segment`
176			`add $10,$0,_bdata ; lowest dst addr to be written to`
177			`add $8,$0,_edata ; one above the top dst addr`
178			`sub $9,$8,$10 ; $9 = size of data segment`
179			`add $9,$9,_ecode ; data is waiting right after code`
180			`j cpytest`
181			`cpyloop:`
182			`ldw $11,$9,0 ; src addr in $9`
183			`stw $11,$8,0 ; dst addr in $8`
184			`cpytest:`
185			`sub $8,$8,4 ; downward`
186			`sub $9,$9,4`
187			`bgeu $8,$10,cpyloop`
188
189			`; clear bss segment`
190			`add $8,$0,_bbss ; start with first word of bss`
191			`add $9,$0,_ebss ; this is one above the top`
192			`j clrtest`
193			`clrloop:`
194			`stw $0,$8,0 ; dst addr in $8`
195			`add $8,$8,4 ; upward`
196			`clrtest:`
197			`bltu $8,$9,clrloop`
198
199			`; now do some useful work`
200			`add $29,$0,stacktop ; setup monitor stack`
201	55	hellwig	`jal dspinit ; init display`
202			`jal kbdinit ; init keyboard`
203	182	hellwig	`jal ser0init ; init serial line 0`
204			`jal ser1init ; init serial line 1`
205			`jal dskinit ; init disk`
206	16	hellwig	`jal main ; enter command loop`
207
208			`; main should never return`
209			`j start ; just to be sure...`
210
211			`;***************************************************************`
212
213	55	hellwig	`.code`
214			`.align 4`
215
216	16	hellwig	`; Word getTLB_HI(int index)`
217			`getTLB_HI:`
218			`mvts $4,TLB_INDEX`
219			`tbri`
220			`mvfs $2,TLB_ENTRY_HI`
221			`jr $31`
222
223			`; Word getTLB_LO(int index)`
224			`getTLB_LO:`
225			`mvts $4,TLB_INDEX`
226			`tbri`
227			`mvfs $2,TLB_ENTRY_LO`
228			`jr $31`
229
230			`; void setTLB(int index, Word entryHi, Word entryLo)`
231			`setTLB:`
232			`mvts $4,TLB_INDEX`
233			`mvts $5,TLB_ENTRY_HI`
234			`mvts $6,TLB_ENTRY_LO`
235			`tbwi`
236			`jr $31`
237
238			`;***************************************************************`
239
240	55	hellwig	`.code`
241			`.align 4`
242
243	16	hellwig	`; int dskcap(int dskno)`
244			`dcap:`
245			`bne $4,$0,dcapser`
246	182	hellwig	`j dskcapctl`
247	16	hellwig	`dcapser:`
248	182	hellwig	`j dskcapser`
249	16	hellwig
250			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
251			`dio:`
252			`bne $4,$0,dioser`
253			`add $4,$5,$0`
254			`add $5,$6,$0`
255			`add $6,$7,$0`
256			`ldw $7,$29,16`
257	182	hellwig	`j dskioctl`
258	16	hellwig	`dioser:`
259			`add $4,$5,$0`
260			`add $5,$6,$0`
261			`add $6,$7,$0`
262			`ldw $7,$29,16`
263	182	hellwig	`j dskioser`
264	16	hellwig
265			`;***************************************************************`
266
267			`.code`
268			`.align 4`
269
270			`; Bool saveState(MonitorState *msp)`
271			`; always return 'true' here`
272			`saveState:`
273			`stw $31,$4,0*4 ; return address`
274			`stw $29,$4,1*4 ; stack pointer`
275			`stw $16,$4,2*4 ; local variables`
276			`stw $17,$4,3*4`
277			`stw $18,$4,4*4`
278			`stw $19,$4,5*4`
279			`stw $20,$4,6*4`
280			`stw $21,$4,7*4`
281			`stw $22,$4,8*4`
282			`stw $23,$4,9*4`
283			`add $2,$0,1`
284			`jr $31`
285
286			`; load state when re-entering monitor`
287			`; this appears as if returning from saveState`
288			`; but the return value is 'false' here`
289			`loadState:`
290			`ldw $8,$0,monitorReturn`
291			`beq $8,$0,loadState ; fatal error: monitor state lost`
292			`ldw $31,$8,0*4 ; return address`
293			`ldw $29,$8,1*4 ; stack pointer`
294			`ldw $16,$8,2*4 ; local variables`
295			`ldw $17,$8,3*4`
296			`ldw $18,$8,4*4`
297			`ldw $19,$8,5*4`
298			`ldw $20,$8,6*4`
299			`ldw $21,$8,7*4`
300			`ldw $22,$8,8*4`
301			`ldw $23,$8,9*4`
302			`add $2,$0,0`
303			`jr $31`
304
305			`.bss`
306			`.align 4`
307
308			`; extern MonitorState *monitorReturn`
309			`monitorReturn:`
310			`.space 4`
311
312			`; extern UserContext userContext`
313			`userContext:`
314			`.space USER_CONTEXT_SIZE`
315
316			`;***************************************************************`
317
318			`.code`
319			`.align 4`
320
321			`; void resume(void)`
322			`; use userContext to load state`
323			`resume:`
324			`mvts $0,PSW`
325			`add $28,$0,userContext`
326			`.nosyn`
327			`ldw $8,$28,33*4 ; tlbIndex`
328			`mvts $8,TLB_INDEX`
329	55	hellwig	`ldw $8,$28,34*4 ; tlbEntryHi`
330	16	hellwig	`mvts $8,TLB_ENTRY_HI`
331			`ldw $8,$28,35*4 ; tlbEntryLo`
332			`mvts $8,TLB_ENTRY_LO`
333	84	hellwig	`ldw $8,$28,36*4 ; badAddress`
334			`mvts $8,BAD_ADDRESS`
335	180	hellwig	`ldw $8,$28,37*4 ; badAccess`
336			`mvts $8,BAD_ACCESS`
337	16	hellwig	`;ldw $0,$28,0*4 ; registers`
338			`ldw $1,$28,1*4`
339			`ldw $2,$28,2*4`
340			`ldw $3,$28,3*4`
341			`ldw $4,$28,4*4`
342			`ldw $5,$28,5*4`
343			`ldw $6,$28,6*4`
344			`ldw $7,$28,7*4`
345			`ldw $8,$28,8*4`
346			`ldw $9,$28,9*4`
347			`ldw $10,$28,10*4`
348			`ldw $11,$28,11*4`
349			`ldw $12,$28,12*4`
350			`ldw $13,$28,13*4`
351			`ldw $14,$28,14*4`
352			`ldw $15,$28,15*4`
353			`ldw $16,$28,16*4`
354			`ldw $17,$28,17*4`
355			`ldw $18,$28,18*4`
356			`ldw $19,$28,19*4`
357			`ldw $20,$28,20*4`
358			`ldw $21,$28,21*4`
359			`ldw $22,$28,22*4`
360			`ldw $23,$28,23*4`
361			`ldw $24,$28,24*4`
362			`ldw $25,$28,25*4`
363			`ldw $26,$28,26*4`
364			`ldw $27,$28,27*4`
365			`;ldw $28,$28,28*4`
366			`ldw $29,$28,29*4`
367			`ldw $30,$28,30*4`
368			`ldw $31,$28,31*4`
369			`ldw $28,$28,32*4 ; psw`
370			`mvts $28,PSW`
371			`rfx`
372			`.syn`
373
374			`; interrupt entry`
375			`; use userContext to store state`
376			`isr:`
377			`umsr:`
378			`.nosyn`
379			`ldhi $28,userContext`
380			`or $28,$28,userContext`
381			`stw $0,$28,0*4 ; registers`
382			`stw $1,$28,1*4`
383			`stw $2,$28,2*4`
384			`stw $3,$28,3*4`
385			`stw $4,$28,4*4`
386			`stw $5,$28,5*4`
387			`stw $6,$28,6*4`
388			`stw $7,$28,7*4`
389			`stw $8,$28,8*4`
390			`stw $9,$28,9*4`
391			`stw $10,$28,10*4`
392			`stw $11,$28,11*4`
393			`stw $12,$28,12*4`
394			`stw $13,$28,13*4`
395			`stw $14,$28,14*4`
396			`stw $15,$28,15*4`
397			`stw $16,$28,16*4`
398			`stw $17,$28,17*4`
399			`stw $18,$28,18*4`
400			`stw $19,$28,19*4`
401			`stw $20,$28,20*4`
402			`stw $21,$28,21*4`
403			`stw $22,$28,22*4`
404			`stw $23,$28,23*4`
405			`stw $24,$28,24*4`
406			`stw $25,$28,25*4`
407			`stw $26,$28,26*4`
408			`stw $27,$28,27*4`
409			`stw $28,$28,28*4`
410			`stw $29,$28,29*4`
411			`stw $30,$28,30*4`
412			`stw $31,$28,31*4`
413			`mvfs $8,PSW`
414			`stw $8,$28,32*4 ; psw`
415			`mvfs $8,TLB_INDEX`
416			`stw $8,$28,33*4 ; tlbIndex`
417			`mvfs $8,TLB_ENTRY_HI`
418			`stw $8,$28,34*4 ; tlbEntryHi`
419			`mvfs $8,TLB_ENTRY_LO`
420			`stw $8,$28,35*4 ; tlbEntryLo`
421	84	hellwig	`mvfs $8,BAD_ADDRESS`
422			`stw $8,$28,36*4 ; badAddress`
423	180	hellwig	`mvfs $8,BAD_ACCESS`
424			`stw $8,$28,37*4 ; badAccess`
425	16	hellwig	`.syn`
426			`j loadState`

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