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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 328

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Line No. Rev Author Line
1 16 hellwig
;
2
; start.s -- ECO32 ROM monitor startup and support routines
3
;
4
 
5 193 hellwig
        .set    BIO_BASE,0xF1000000     ; board I/O base address
6
        .set    BIO_WR,BIO_BASE+0
7
        .set    BIO_RD,BIO_BASE+4
8
        .set    CIO_CTRL,0x08           ; this bit controls console I/O
9 185 hellwig
 
10 193 hellwig
        .set    CIO_KBD_DSP,0x00        ; set console to keyboard/display
11
        .set    CIO_SERIAL_0,0x03       ; set console to serial line 0
12
 
13 16 hellwig
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
14 55 hellwig
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
15 16 hellwig
 
16
        .set    PSW,0                    ; reg # of PSW
17 55 hellwig
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
18
        .set    V,1 << V_SHIFT
19
 
20 16 hellwig
        .set    TLB_INDEX,1             ; reg # of TLB Index
21
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
22
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
23
        .set    TLB_ENTRIES,32          ; number of TLB entries
24 84 hellwig
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
25 180 hellwig
        .set    BAD_ACCESS,5            ; reg # of bad access reg
26 16 hellwig
 
27 180 hellwig
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
28 16 hellwig
 
29
;***************************************************************
30
 
31
        .import _ecode
32
        .import _edata
33
        .import _ebss
34
 
35 185 hellwig
        .import kbdinit
36
        .import kbdinchk
37
        .import kbdin
38
 
39 182 hellwig
        .import dspinit
40
        .import dspoutchk
41
        .import dspout
42
 
43
        .import ser0init
44 16 hellwig
        .import ser0inchk
45
        .import ser0in
46
        .import ser0outchk
47
        .import ser0out
48
 
49 182 hellwig
        .import ser1init
50
        .import ser1inchk
51
        .import ser1in
52
        .import ser1outchk
53
        .import ser1out
54 16 hellwig
 
55 184 hellwig
        .import dskinitctl
56 182 hellwig
        .import dskcapctl
57
        .import dskioctl
58 184 hellwig
 
59
        .import dskinitser
60 182 hellwig
        .import dskcapser
61
        .import dskioser
62
 
63 16 hellwig
        .import main
64
 
65
        .export _bcode
66
        .export _bdata
67
        .export _bbss
68
 
69 185 hellwig
        .export setcon
70 16 hellwig
        .export cinchk
71
        .export cin
72
        .export coutchk
73
        .export cout
74
        .export dskcap
75
        .export dskio
76
 
77
        .export getTLB_HI
78
        .export getTLB_LO
79
        .export setTLB
80
 
81
        .export saveState
82
        .export monitorReturn
83
 
84
        .import userContext
85
        .export resume
86
 
87
;***************************************************************
88
 
89
        .code
90
_bcode:
91
 
92
        .data
93
_bdata:
94
 
95
        .bss
96
_bbss:
97
 
98
;***************************************************************
99
 
100
        .code
101
        .align  4
102
 
103 185 hellwig
startup:
104 16 hellwig
        j       start
105
 
106
interrupt:
107 200 hellwig
        j       debug
108 16 hellwig
 
109
userMiss:
110 200 hellwig
        j       debug
111 16 hellwig
 
112 200 hellwig
monitor:
113
        j       debug
114
 
115 16 hellwig
;***************************************************************
116
 
117
        .code
118
        .align  4
119
 
120 185 hellwig
setcon:
121
        j       setcio
122
 
123 16 hellwig
cinchk:
124 185 hellwig
        j       cichk
125 16 hellwig
 
126
cin:
127 185 hellwig
        j       ci
128 16 hellwig
 
129
coutchk:
130 185 hellwig
        j       cochk
131 16 hellwig
 
132
cout:
133 185 hellwig
        j       co
134 16 hellwig
 
135
dskcap:
136
        j       dcap
137
 
138
dskio:
139
        j       dio
140
 
141 200 hellwig
reserved_11:
142
        j       reserved_11
143 55 hellwig
 
144 200 hellwig
reserved_12:
145
        j       reserved_12
146 55 hellwig
 
147 200 hellwig
reserved_13:
148
        j       reserved_13
149 55 hellwig
 
150 200 hellwig
reserved_14:
151
        j       reserved_14
152 185 hellwig
 
153 200 hellwig
reserved_15:
154
        j       reserved_15
155 185 hellwig
 
156 16 hellwig
;***************************************************************
157
 
158
        .code
159
        .align  4
160
 
161
start:
162 55 hellwig
        ; let irq/exc vectors point to RAM
163
        add     $8,$0,V
164
        mvts    $8,PSW
165 16 hellwig
 
166
        ; initialize TLB
167
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
168
        add     $8,$0,dmapaddr           ; by impossible virtual page number
169 182 hellwig
        mvts    $8,TLB_ENTRY_HI
170
        add     $8,$0,$0
171
        add     $9,$0,TLB_ENTRIES
172 16 hellwig
tlbloop:
173 182 hellwig
        mvts    $8,TLB_INDEX
174 16 hellwig
        tbwi
175 182 hellwig
        add     $8,$8,1
176
        bne     $8,$9,tlbloop
177 16 hellwig
 
178
        ; copy data segment
179
        add     $10,$0,_bdata            ; lowest dst addr to be written to
180
        add     $8,$0,_edata             ; one above the top dst addr
181
        sub     $9,$8,$10               ; $9 = size of data segment
182
        add     $9,$9,_ecode            ; data is waiting right after code
183
        j       cpytest
184
cpyloop:
185
        ldw     $11,$9,0         ; src addr in $9
186
        stw     $11,$8,0         ; dst addr in $8
187
cpytest:
188
        sub     $8,$8,4                 ; downward
189
        sub     $9,$9,4
190
        bgeu    $8,$10,cpyloop
191
 
192
        ; clear bss segment
193
        add     $8,$0,_bbss              ; start with first word of bss
194
        add     $9,$0,_ebss              ; this is one above the top
195
        j       clrtest
196
clrloop:
197
        stw     $0,$8,0                   ; dst addr in $8
198
        add     $8,$8,4                 ; upward
199
clrtest:
200
        bltu    $8,$9,clrloop
201
 
202 185 hellwig
        ; initialize I/O
203 16 hellwig
        add     $29,$0,stacktop          ; setup monitor stack
204 185 hellwig
        jal     kbdinit                 ; init keyboard
205 55 hellwig
        jal     dspinit                 ; init display
206 182 hellwig
        jal     ser0init                ; init serial line 0
207
        jal     ser1init                ; init serial line 1
208 184 hellwig
        jal     dskinitctl              ; init disk (controller)
209
        jal     dskinitser              ; init disk (serial line)
210 193 hellwig
        ldw     $8,$0,BIO_RD             ; get switch settings
211
        and     $8,$8,CIO_CTRL
212
        add     $4,$0,CIO_SERIAL_0       ; set console to serial line
213
        bne     $8,$0,swtchset
214
        add     $4,$0,CIO_KBD_DSP        ; set console to kbd/dsp
215
swtchset:
216 185 hellwig
        jal     setcio
217
 
218
        ; call main
219 16 hellwig
        jal     main                    ; enter command loop
220
 
221
        ; main should never return
222
        j       start                   ; just to be sure...
223
 
224
;***************************************************************
225
 
226 55 hellwig
        .code
227
        .align  4
228
 
229 16 hellwig
        ; Word getTLB_HI(int index)
230
getTLB_HI:
231
        mvts    $4,TLB_INDEX
232
        tbri
233
        mvfs    $2,TLB_ENTRY_HI
234
        jr      $31
235
 
236
        ; Word getTLB_LO(int index)
237
getTLB_LO:
238
        mvts    $4,TLB_INDEX
239
        tbri
240
        mvfs    $2,TLB_ENTRY_LO
241
        jr      $31
242
 
243
        ; void setTLB(int index, Word entryHi, Word entryLo)
244
setTLB:
245
        mvts    $4,TLB_INDEX
246
        mvts    $5,TLB_ENTRY_HI
247
        mvts    $6,TLB_ENTRY_LO
248
        tbwi
249
        jr      $31
250
 
251
;***************************************************************
252
 
253 185 hellwig
        .data
254
        .align  4
255
 
256
cioctl:
257
        .byte   0
258
 
259 55 hellwig
        .code
260
        .align  4
261
 
262 185 hellwig
        ; void setcon(Byte ctl)
263
setcio:
264
        stb     $4,$0,cioctl
265
        j       $31
266
 
267
        ; int cinchk(void)
268
cichk:
269
        ldbu    $8,$0,cioctl
270
        and     $8,$8,0x01
271
        bne     $8,$0,cichk1
272
        j       kbdinchk
273
cichk1:
274
        j       ser0inchk
275
 
276
        ; char cin(void)
277
ci:
278
        ldbu    $8,$0,cioctl
279
        and     $8,$8,0x01
280
        bne     $8,$0,ci1
281
        j       kbdin
282
ci1:
283
        j       ser0in
284
 
285
        ; int coutchk(void)
286
cochk:
287
        ldbu    $8,$0,cioctl
288
        and     $8,$8,0x02
289
        bne     $8,$0,cochk1
290
        j       dspoutchk
291
cochk1:
292
        j       ser0outchk
293
 
294
        ; void cout(char c)
295
co:
296
        ldbu    $8,$0,cioctl
297
        and     $8,$8,0x02
298
        bne     $8,$0,co1
299
        j       dspout
300
co1:
301
        j       ser0out
302
 
303
;***************************************************************
304
 
305
        .code
306
        .align  4
307
 
308 16 hellwig
        ; int dskcap(int dskno)
309
dcap:
310
        bne     $4,$0,dcapser
311 182 hellwig
        j       dskcapctl
312 16 hellwig
dcapser:
313 182 hellwig
        j       dskcapser
314 16 hellwig
 
315
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
316
dio:
317
        bne     $4,$0,dioser
318
        add     $4,$5,$0
319
        add     $5,$6,$0
320
        add     $6,$7,$0
321
        ldw     $7,$29,16
322 182 hellwig
        j       dskioctl
323 16 hellwig
dioser:
324
        add     $4,$5,$0
325
        add     $5,$6,$0
326
        add     $6,$7,$0
327
        ldw     $7,$29,16
328 182 hellwig
        j       dskioser
329 16 hellwig
 
330
;***************************************************************
331
 
332
        .code
333
        .align  4
334
 
335
        ; Bool saveState(MonitorState *msp)
336
        ; always return 'true' here
337
saveState:
338
        stw     $31,$4,0*4               ; return address
339
        stw     $29,$4,1*4              ; stack pointer
340
        stw     $16,$4,2*4              ; local variables
341
        stw     $17,$4,3*4
342
        stw     $18,$4,4*4
343
        stw     $19,$4,5*4
344
        stw     $20,$4,6*4
345
        stw     $21,$4,7*4
346
        stw     $22,$4,8*4
347
        stw     $23,$4,9*4
348
        add     $2,$0,1
349
        jr      $31
350
 
351
        ; load state when re-entering monitor
352
        ; this appears as if returning from saveState
353
        ; but the return value is 'false' here
354
loadState:
355
        ldw     $8,$0,monitorReturn
356
        beq     $8,$0,loadState          ; fatal error: monitor state lost
357
        ldw     $31,$8,0*4               ; return address
358
        ldw     $29,$8,1*4              ; stack pointer
359
        ldw     $16,$8,2*4              ; local variables
360
        ldw     $17,$8,3*4
361
        ldw     $18,$8,4*4
362
        ldw     $19,$8,5*4
363
        ldw     $20,$8,6*4
364
        ldw     $21,$8,7*4
365
        ldw     $22,$8,8*4
366
        ldw     $23,$8,9*4
367
        add     $2,$0,0
368
        jr      $31
369
 
370
        .bss
371
        .align  4
372
 
373
        ; extern MonitorState *monitorReturn
374
monitorReturn:
375
        .space  4
376
 
377
        ; extern UserContext userContext
378
userContext:
379
        .space  USER_CONTEXT_SIZE
380
 
381
;***************************************************************
382
 
383
        .code
384
        .align  4
385
 
386
        ; void resume(void)
387
        ; use userContext to load state
388
resume:
389
        mvts    $0,PSW
390 201 hellwig
        add     $24,$0,userContext
391 16 hellwig
        .nosyn
392 201 hellwig
        ldw     $8,$24,33*4             ; tlbIndex
393 16 hellwig
        mvts    $8,TLB_INDEX
394 201 hellwig
        ldw     $8,$24,34*4             ; tlbEntryHi
395 16 hellwig
        mvts    $8,TLB_ENTRY_HI
396 201 hellwig
        ldw     $8,$24,35*4             ; tlbEntryLo
397 16 hellwig
        mvts    $8,TLB_ENTRY_LO
398 201 hellwig
        ldw     $8,$24,36*4             ; badAddress
399 84 hellwig
        mvts    $8,BAD_ADDRESS
400 201 hellwig
        ldw     $8,$24,37*4             ; badAccess
401 180 hellwig
        mvts    $8,BAD_ACCESS
402 201 hellwig
        ;ldw    $0,$24,0*4              ; registers
403
        ldw     $1,$24,1*4
404
        ldw     $2,$24,2*4
405
        ldw     $3,$24,3*4
406
        ldw     $4,$24,4*4
407
        ldw     $5,$24,5*4
408
        ldw     $6,$24,6*4
409
        ldw     $7,$24,7*4
410
        ldw     $8,$24,8*4
411
        ldw     $9,$24,9*4
412
        ldw     $10,$24,10*4
413
        ldw     $11,$24,11*4
414
        ldw     $12,$24,12*4
415
        ldw     $13,$24,13*4
416
        ldw     $14,$24,14*4
417
        ldw     $15,$24,15*4
418
        ldw     $16,$24,16*4
419
        ldw     $17,$24,17*4
420
        ldw     $18,$24,18*4
421
        ldw     $19,$24,19*4
422
        ldw     $20,$24,20*4
423
        ldw     $21,$24,21*4
424
        ldw     $22,$24,22*4
425
        ldw     $23,$24,23*4
426
        ;ldw    $24,$24,24*4
427
        ldw     $25,$24,25*4
428
        ldw     $26,$24,26*4
429
        ldw     $27,$24,27*4
430
        ldw     $28,$24,28*4
431
        ldw     $29,$24,29*4
432
        ldw     $30,$24,30*4
433
        ldw     $31,$24,31*4
434
        ldw     $24,$24,32*4            ; psw
435
        mvts    $24,PSW
436 16 hellwig
        rfx
437
        .syn
438
 
439 200 hellwig
        ; debug entry
440 16 hellwig
        ; use userContext to store state
441 200 hellwig
debug:
442 16 hellwig
        .nosyn
443 201 hellwig
        ldhi    $24,userContext
444
        or      $24,$24,userContext
445
        stw     $0,$24,0*4                ; registers
446
        stw     $1,$24,1*4
447
        stw     $2,$24,2*4
448
        stw     $3,$24,3*4
449
        stw     $4,$24,4*4
450
        stw     $5,$24,5*4
451
        stw     $6,$24,6*4
452
        stw     $7,$24,7*4
453
        stw     $8,$24,8*4
454
        stw     $9,$24,9*4
455
        stw     $10,$24,10*4
456
        stw     $11,$24,11*4
457
        stw     $12,$24,12*4
458
        stw     $13,$24,13*4
459
        stw     $14,$24,14*4
460
        stw     $15,$24,15*4
461
        stw     $16,$24,16*4
462
        stw     $17,$24,17*4
463
        stw     $18,$24,18*4
464
        stw     $19,$24,19*4
465
        stw     $20,$24,20*4
466
        stw     $21,$24,21*4
467
        stw     $22,$24,22*4
468
        stw     $23,$24,23*4
469
        stw     $24,$24,24*4
470
        stw     $25,$24,25*4
471
        stw     $26,$24,26*4
472
        stw     $27,$24,27*4
473
        stw     $28,$24,28*4
474
        stw     $29,$24,29*4
475
        stw     $30,$24,30*4
476
        stw     $31,$24,31*4
477 16 hellwig
        mvfs    $8,PSW
478 201 hellwig
        stw     $8,$24,32*4             ; psw
479 16 hellwig
        mvfs    $8,TLB_INDEX
480 201 hellwig
        stw     $8,$24,33*4             ; tlbIndex
481 16 hellwig
        mvfs    $8,TLB_ENTRY_HI
482 201 hellwig
        stw     $8,$24,34*4             ; tlbEntryHi
483 16 hellwig
        mvfs    $8,TLB_ENTRY_LO
484 201 hellwig
        stw     $8,$24,35*4             ; tlbEntryLo
485 84 hellwig
        mvfs    $8,BAD_ADDRESS
486 201 hellwig
        stw     $8,$24,36*4             ; badAddress
487 180 hellwig
        mvfs    $8,BAD_ACCESS
488 201 hellwig
        stw     $8,$24,37*4             ; badAccess
489 16 hellwig
        .syn
490
        j       loadState

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