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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 331

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    BIO_BASE,0xF1000000     ; board I/O base address
        .set    BIO_WR,BIO_BASE+0
        .set    BIO_RD,BIO_BASE+4
        .set    CIO_CTRL,0x08           ; this bit controls console I/O
 
        .set    CIO_KBD_DSP,0x00        ; set console to keyboard/display
        .set    CIO_SERIAL_0,0x03       ; set console to serial line 0
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
        .set    BAD_ADDRESS,4           ; reg # of bad address reg
        .set    BAD_ACCESS,5            ; reg # of bad access reg
 
        .set    USER_CONTEXT_SIZE,38*4  ; size of user context
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import ser0init
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import ser1init
        .import ser1inchk
        .import ser1in
        .import ser1outchk
        .import ser1out
 
        .import dskinitctl
        .import dskcapctl
        .import dskioctl
 
        .import dskinitser
        .import dskcapser
        .import dskioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export setcon
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export dskcap
        .export dskio
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
startup:
        j       start
 
interrupt:
        j       debug
 
userMiss:
        j       debug
 
monitor:
        j       debug
 
;***************************************************************
 
        .code
        .align  4
 
setcon:
        j       setcio
 
cinchk:
        j       cichk
 
cin:
        j       ci
 
coutchk:
        j       cochk
 
cout:
        j       co
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved_11:
        j       reserved_11
 
reserved_12:
        j       reserved_12
 
reserved_13:
        j       reserved_13
 
reserved_14:
        j       reserved_14
 
reserved_15:
        j       reserved_15
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        mvts    $8,TLB_ENTRY_HI
        add     $8,$0,$0
        add     $9,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_INDEX
        tbwi
        add     $8,$8,1
        bne     $8,$9,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; initialize I/O
        add     $29,$0,stacktop          ; setup monitor stack
        ldw     $8,$0,BIO_RD             ; get switch settings
        and     $8,$8,CIO_CTRL
        add     $4,$0,CIO_SERIAL_0       ; set console to serial line
        bne     $8,$0,swtchset
        add     $4,$0,CIO_KBD_DSP        ; set console to kbd/dsp
swtchset:
        jal     setcio
        ldbu    $8,$0,cioctl             ; get control byte
        and     $8,$8,0x01              ; keyboard input wanted?
        bne     $8,$0,nokbd              ; no - then don't touch
        jal     kbdinit                 ; else init keyboard
nokbd:
        ldbu    $8,$0,cioctl             ; get control byte
        and     $8,$8,0x02              ; display output wanted?
        bne     $8,$0,nodsp              ; no - then don't touch
        jal     dspinit                 ; else init display
nodsp:
        jal     ser0init                ; init serial line 0
        jal     ser1init                ; init serial line 1
        jal     dskinitctl              ; init disk (controller)
        jal     dskinitser              ; init disk (serial line)
 
        ; call main
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .data
        .align  4
 
cioctl:
        .byte   0
 
        .code
        .align  4
 
        ; void setcon(Byte ctl)
setcio:
        stb     $4,$0,cioctl
        j       $31
 
        ; int cinchk(void)
cichk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,cichk1
        j       kbdinchk
cichk1:
        j       ser0inchk
 
        ; char cin(void)
ci:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x01
        bne     $8,$0,ci1
        j       kbdin
ci1:
        j       ser0in
 
        ; int coutchk(void)
cochk:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,cochk1
        j       dspoutchk
cochk1:
        j       ser0outchk
 
        ; void cout(char c)
co:
        ldbu    $8,$0,cioctl
        and     $8,$8,0x02
        bne     $8,$0,co1
        j       dspout
co1:
        j       ser0out
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       dskcapctl
dcapser:
        j       dskcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       dskioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $24,$0,userContext
        .nosyn
        ldw     $8,$24,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$24,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$24,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ldw     $8,$24,36*4             ; badAddress
        mvts    $8,BAD_ADDRESS
        ldw     $8,$24,37*4             ; badAccess
        mvts    $8,BAD_ACCESS
        ;ldw    $0,$24,0*4              ; registers
        ldw     $1,$24,1*4
        ldw     $2,$24,2*4
        ldw     $3,$24,3*4
        ldw     $4,$24,4*4
        ldw     $5,$24,5*4
        ldw     $6,$24,6*4
        ldw     $7,$24,7*4
        ldw     $8,$24,8*4
        ldw     $9,$24,9*4
        ldw     $10,$24,10*4
        ldw     $11,$24,11*4
        ldw     $12,$24,12*4
        ldw     $13,$24,13*4
        ldw     $14,$24,14*4
        ldw     $15,$24,15*4
        ldw     $16,$24,16*4
        ldw     $17,$24,17*4
        ldw     $18,$24,18*4
        ldw     $19,$24,19*4
        ldw     $20,$24,20*4
        ldw     $21,$24,21*4
        ldw     $22,$24,22*4
        ldw     $23,$24,23*4
        ;ldw    $24,$24,24*4
        ldw     $25,$24,25*4
        ldw     $26,$24,26*4
        ldw     $27,$24,27*4
        ldw     $28,$24,28*4
        ldw     $29,$24,29*4
        ldw     $30,$24,30*4
        ldw     $31,$24,31*4
        ldw     $24,$24,32*4            ; psw
        mvts    $24,PSW
        rfx
        .syn
 
        ; debug entry
        ; use userContext to store state
debug:
        .nosyn
        ldhi    $24,userContext
        or      $24,$24,userContext
        stw     $0,$24,0*4                ; registers
        stw     $1,$24,1*4
        stw     $2,$24,2*4
        stw     $3,$24,3*4
        stw     $4,$24,4*4
        stw     $5,$24,5*4
        stw     $6,$24,6*4
        stw     $7,$24,7*4
        stw     $8,$24,8*4
        stw     $9,$24,9*4
        stw     $10,$24,10*4
        stw     $11,$24,11*4
        stw     $12,$24,12*4
        stw     $13,$24,13*4
        stw     $14,$24,14*4
        stw     $15,$24,15*4
        stw     $16,$24,16*4
        stw     $17,$24,17*4
        stw     $18,$24,18*4
        stw     $19,$24,19*4
        stw     $20,$24,20*4
        stw     $21,$24,21*4
        stw     $22,$24,22*4
        stw     $23,$24,23*4
        stw     $24,$24,24*4
        stw     $25,$24,25*4
        stw     $26,$24,26*4
        stw     $27,$24,27*4
        stw     $28,$24,28*4
        stw     $29,$24,29*4
        stw     $30,$24,30*4
        stw     $31,$24,31*4
        mvfs    $8,PSW
        stw     $8,$24,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$24,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$24,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$24,35*4             ; tlbEntryLo
        mvfs    $8,BAD_ADDRESS
        stw     $8,$24,36*4             ; badAddress
        mvfs    $8,BAD_ACCESS
        stw     $8,$24,37*4             ; badAccess
        .syn
        j       loadState

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5	193	hellwig	`.set BIO_BASE,0xF1000000 ; board I/O base address`
6			`.set BIO_WR,BIO_BASE+0`
7			`.set BIO_RD,BIO_BASE+4`
8			`.set CIO_CTRL,0x08 ; this bit controls console I/O`
9	185	hellwig
10	193	hellwig	`.set CIO_KBD_DSP,0x00 ; set console to keyboard/display`
11			`.set CIO_SERIAL_0,0x03 ; set console to serial line 0`
12
13	16	hellwig	`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
14	55	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
15	16	hellwig
16			`.set PSW,0 ; reg # of PSW`
17	55	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
18			`.set V,1 << V_SHIFT`
19
20	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
21			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
22			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
23			`.set TLB_ENTRIES,32 ; number of TLB entries`
24	84	hellwig	`.set BAD_ADDRESS,4 ; reg # of bad address reg`
25	180	hellwig	`.set BAD_ACCESS,5 ; reg # of bad access reg`
26	16	hellwig
27	180	hellwig	`.set USER_CONTEXT_SIZE,38*4 ; size of user context`
28	16	hellwig
29			`;***************************************************************`
30
31			`.import _ecode`
32			`.import _edata`
33			`.import _ebss`
34
35	185	hellwig	`.import kbdinit`
36			`.import kbdinchk`
37			`.import kbdin`
38
39	182	hellwig	`.import dspinit`
40			`.import dspoutchk`
41			`.import dspout`
42
43			`.import ser0init`
44	16	hellwig	`.import ser0inchk`
45			`.import ser0in`
46			`.import ser0outchk`
47			`.import ser0out`
48
49	182	hellwig	`.import ser1init`
50			`.import ser1inchk`
51			`.import ser1in`
52			`.import ser1outchk`
53			`.import ser1out`
54	16	hellwig
55	184	hellwig	`.import dskinitctl`
56	182	hellwig	`.import dskcapctl`
57			`.import dskioctl`
58	184	hellwig
59			`.import dskinitser`
60	182	hellwig	`.import dskcapser`
61			`.import dskioser`
62
63	16	hellwig	`.import main`
64
65			`.export _bcode`
66			`.export _bdata`
67			`.export _bbss`
68
69	185	hellwig	`.export setcon`
70	16	hellwig	`.export cinchk`
71			`.export cin`
72			`.export coutchk`
73			`.export cout`
74			`.export dskcap`
75			`.export dskio`
76
77			`.export getTLB_HI`
78			`.export getTLB_LO`
79			`.export setTLB`
80
81			`.export saveState`
82			`.export monitorReturn`
83
84			`.import userContext`
85			`.export resume`
86
87			`;***************************************************************`
88
89			`.code`
90			`_bcode:`
91
92			`.data`
93			`_bdata:`
94
95			`.bss`
96			`_bbss:`
97
98			`;***************************************************************`
99
100			`.code`
101			`.align 4`
102
103	185	hellwig	`startup:`
104	16	hellwig	`j start`
105
106			`interrupt:`
107	200	hellwig	`j debug`
108	16	hellwig
109			`userMiss:`
110	200	hellwig	`j debug`
111	16	hellwig
112	200	hellwig	`monitor:`
113			`j debug`
114
115	16	hellwig	`;***************************************************************`
116
117			`.code`
118			`.align 4`
119
120	185	hellwig	`setcon:`
121			`j setcio`
122
123	16	hellwig	`cinchk:`
124	185	hellwig	`j cichk`
125	16	hellwig
126			`cin:`
127	185	hellwig	`j ci`
128	16	hellwig
129			`coutchk:`
130	185	hellwig	`j cochk`
131	16	hellwig
132			`cout:`
133	185	hellwig	`j co`
134	16	hellwig
135			`dskcap:`
136			`j dcap`
137
138			`dskio:`
139			`j dio`
140
141	200	hellwig	`reserved_11:`
142			`j reserved_11`
143	55	hellwig
144	200	hellwig	`reserved_12:`
145			`j reserved_12`
146	55	hellwig
147	200	hellwig	`reserved_13:`
148			`j reserved_13`
149	55	hellwig
150	200	hellwig	`reserved_14:`
151			`j reserved_14`
152	185	hellwig
153	200	hellwig	`reserved_15:`
154			`j reserved_15`
155	185	hellwig
156	16	hellwig	`;***************************************************************`
157
158			`.code`
159			`.align 4`
160
161			`start:`
162	55	hellwig	`; let irq/exc vectors point to RAM`
163			`add $8,$0,V`
164			`mvts $8,PSW`
165	16	hellwig
166			`; initialize TLB`
167			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
168			`add $8,$0,dmapaddr ; by impossible virtual page number`
169	182	hellwig	`mvts $8,TLB_ENTRY_HI`
170			`add $8,$0,$0`
171			`add $9,$0,TLB_ENTRIES`
172	16	hellwig	`tlbloop:`
173	182	hellwig	`mvts $8,TLB_INDEX`
174	16	hellwig	`tbwi`
175	182	hellwig	`add $8,$8,1`
176			`bne $8,$9,tlbloop`
177	16	hellwig
178			`; copy data segment`
179			`add $10,$0,_bdata ; lowest dst addr to be written to`
180			`add $8,$0,_edata ; one above the top dst addr`
181			`sub $9,$8,$10 ; $9 = size of data segment`
182			`add $9,$9,_ecode ; data is waiting right after code`
183			`j cpytest`
184			`cpyloop:`
185			`ldw $11,$9,0 ; src addr in $9`
186			`stw $11,$8,0 ; dst addr in $8`
187			`cpytest:`
188			`sub $8,$8,4 ; downward`
189			`sub $9,$9,4`
190			`bgeu $8,$10,cpyloop`
191
192			`; clear bss segment`
193			`add $8,$0,_bbss ; start with first word of bss`
194			`add $9,$0,_ebss ; this is one above the top`
195			`j clrtest`
196			`clrloop:`
197			`stw $0,$8,0 ; dst addr in $8`
198			`add $8,$8,4 ; upward`
199			`clrtest:`
200			`bltu $8,$9,clrloop`
201
202	185	hellwig	`; initialize I/O`
203	16	hellwig	`add $29,$0,stacktop ; setup monitor stack`
204	193	hellwig	`ldw $8,$0,BIO_RD ; get switch settings`
205			`and $8,$8,CIO_CTRL`
206			`add $4,$0,CIO_SERIAL_0 ; set console to serial line`
207			`bne $8,$0,swtchset`
208			`add $4,$0,CIO_KBD_DSP ; set console to kbd/dsp`
209			`swtchset:`
210	185	hellwig	`jal setcio`
211	331	hellwig	`ldbu $8,$0,cioctl ; get control byte`
212			`and $8,$8,0x01 ; keyboard input wanted?`
213			`bne $8,$0,nokbd ; no - then don't touch`
214			`jal kbdinit ; else init keyboard`
215			`nokbd:`
216			`ldbu $8,$0,cioctl ; get control byte`
217			`and $8,$8,0x02 ; display output wanted?`
218			`bne $8,$0,nodsp ; no - then don't touch`
219			`jal dspinit ; else init display`
220			`nodsp:`
221			`jal ser0init ; init serial line 0`
222			`jal ser1init ; init serial line 1`
223			`jal dskinitctl ; init disk (controller)`
224			`jal dskinitser ; init disk (serial line)`
225	185	hellwig
226			`; call main`
227	16	hellwig	`jal main ; enter command loop`
228
229			`; main should never return`
230			`j start ; just to be sure...`
231
232			`;***************************************************************`
233
234	55	hellwig	`.code`
235			`.align 4`
236
237	16	hellwig	`; Word getTLB_HI(int index)`
238			`getTLB_HI:`
239			`mvts $4,TLB_INDEX`
240			`tbri`
241			`mvfs $2,TLB_ENTRY_HI`
242			`jr $31`
243
244			`; Word getTLB_LO(int index)`
245			`getTLB_LO:`
246			`mvts $4,TLB_INDEX`
247			`tbri`
248			`mvfs $2,TLB_ENTRY_LO`
249			`jr $31`
250
251			`; void setTLB(int index, Word entryHi, Word entryLo)`
252			`setTLB:`
253			`mvts $4,TLB_INDEX`
254			`mvts $5,TLB_ENTRY_HI`
255			`mvts $6,TLB_ENTRY_LO`
256			`tbwi`
257			`jr $31`
258
259			`;***************************************************************`
260
261	185	hellwig	`.data`
262			`.align 4`
263
264			`cioctl:`
265			`.byte 0`
266
267	55	hellwig	`.code`
268			`.align 4`
269
270	185	hellwig	`; void setcon(Byte ctl)`
271			`setcio:`
272			`stb $4,$0,cioctl`
273			`j $31`
274
275			`; int cinchk(void)`
276			`cichk:`
277			`ldbu $8,$0,cioctl`
278			`and $8,$8,0x01`
279			`bne $8,$0,cichk1`
280			`j kbdinchk`
281			`cichk1:`
282			`j ser0inchk`
283
284			`; char cin(void)`
285			`ci:`
286			`ldbu $8,$0,cioctl`
287			`and $8,$8,0x01`
288			`bne $8,$0,ci1`
289			`j kbdin`
290			`ci1:`
291			`j ser0in`
292
293			`; int coutchk(void)`
294			`cochk:`
295			`ldbu $8,$0,cioctl`
296			`and $8,$8,0x02`
297			`bne $8,$0,cochk1`
298			`j dspoutchk`
299			`cochk1:`
300			`j ser0outchk`
301
302			`; void cout(char c)`
303			`co:`
304			`ldbu $8,$0,cioctl`
305			`and $8,$8,0x02`
306			`bne $8,$0,co1`
307			`j dspout`
308			`co1:`
309			`j ser0out`
310
311			`;***************************************************************`
312
313			`.code`
314			`.align 4`
315
316	16	hellwig	`; int dskcap(int dskno)`
317			`dcap:`
318			`bne $4,$0,dcapser`
319	182	hellwig	`j dskcapctl`
320	16	hellwig	`dcapser:`
321	182	hellwig	`j dskcapser`
322	16	hellwig
323			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
324			`dio:`
325			`bne $4,$0,dioser`
326			`add $4,$5,$0`
327			`add $5,$6,$0`
328			`add $6,$7,$0`
329			`ldw $7,$29,16`
330	182	hellwig	`j dskioctl`
331	16	hellwig	`dioser:`
332			`add $4,$5,$0`
333			`add $5,$6,$0`
334			`add $6,$7,$0`
335			`ldw $7,$29,16`
336	182	hellwig	`j dskioser`
337	16	hellwig
338			`;***************************************************************`
339
340			`.code`
341			`.align 4`
342
343			`; Bool saveState(MonitorState *msp)`
344			`; always return 'true' here`
345			`saveState:`
346			`stw $31,$4,0*4 ; return address`
347			`stw $29,$4,1*4 ; stack pointer`
348			`stw $16,$4,2*4 ; local variables`
349			`stw $17,$4,3*4`
350			`stw $18,$4,4*4`
351			`stw $19,$4,5*4`
352			`stw $20,$4,6*4`
353			`stw $21,$4,7*4`
354			`stw $22,$4,8*4`
355			`stw $23,$4,9*4`
356			`add $2,$0,1`
357			`jr $31`
358
359			`; load state when re-entering monitor`
360			`; this appears as if returning from saveState`
361			`; but the return value is 'false' here`
362			`loadState:`
363			`ldw $8,$0,monitorReturn`
364			`beq $8,$0,loadState ; fatal error: monitor state lost`
365			`ldw $31,$8,0*4 ; return address`
366			`ldw $29,$8,1*4 ; stack pointer`
367			`ldw $16,$8,2*4 ; local variables`
368			`ldw $17,$8,3*4`
369			`ldw $18,$8,4*4`
370			`ldw $19,$8,5*4`
371			`ldw $20,$8,6*4`
372			`ldw $21,$8,7*4`
373			`ldw $22,$8,8*4`
374			`ldw $23,$8,9*4`
375			`add $2,$0,0`
376			`jr $31`
377
378			`.bss`
379			`.align 4`
380
381			`; extern MonitorState *monitorReturn`
382			`monitorReturn:`
383			`.space 4`
384
385			`; extern UserContext userContext`
386			`userContext:`
387			`.space USER_CONTEXT_SIZE`
388
389			`;***************************************************************`
390
391			`.code`
392			`.align 4`
393
394			`; void resume(void)`
395			`; use userContext to load state`
396			`resume:`
397			`mvts $0,PSW`
398	201	hellwig	`add $24,$0,userContext`
399	16	hellwig	`.nosyn`
400	201	hellwig	`ldw $8,$24,33*4 ; tlbIndex`
401	16	hellwig	`mvts $8,TLB_INDEX`
402	201	hellwig	`ldw $8,$24,34*4 ; tlbEntryHi`
403	16	hellwig	`mvts $8,TLB_ENTRY_HI`
404	201	hellwig	`ldw $8,$24,35*4 ; tlbEntryLo`
405	16	hellwig	`mvts $8,TLB_ENTRY_LO`
406	201	hellwig	`ldw $8,$24,36*4 ; badAddress`
407	84	hellwig	`mvts $8,BAD_ADDRESS`
408	201	hellwig	`ldw $8,$24,37*4 ; badAccess`
409	180	hellwig	`mvts $8,BAD_ACCESS`
410	201	hellwig	`;ldw $0,$24,0*4 ; registers`
411			`ldw $1,$24,1*4`
412			`ldw $2,$24,2*4`
413			`ldw $3,$24,3*4`
414			`ldw $4,$24,4*4`
415			`ldw $5,$24,5*4`
416			`ldw $6,$24,6*4`
417			`ldw $7,$24,7*4`
418			`ldw $8,$24,8*4`
419			`ldw $9,$24,9*4`
420			`ldw $10,$24,10*4`
421			`ldw $11,$24,11*4`
422			`ldw $12,$24,12*4`
423			`ldw $13,$24,13*4`
424			`ldw $14,$24,14*4`
425			`ldw $15,$24,15*4`
426			`ldw $16,$24,16*4`
427			`ldw $17,$24,17*4`
428			`ldw $18,$24,18*4`
429			`ldw $19,$24,19*4`
430			`ldw $20,$24,20*4`
431			`ldw $21,$24,21*4`
432			`ldw $22,$24,22*4`
433			`ldw $23,$24,23*4`
434			`;ldw $24,$24,24*4`
435			`ldw $25,$24,25*4`
436			`ldw $26,$24,26*4`
437			`ldw $27,$24,27*4`
438			`ldw $28,$24,28*4`
439			`ldw $29,$24,29*4`
440			`ldw $30,$24,30*4`
441			`ldw $31,$24,31*4`
442			`ldw $24,$24,32*4 ; psw`
443			`mvts $24,PSW`
444	16	hellwig	`rfx`
445			`.syn`
446
447	200	hellwig	`; debug entry`
448	16	hellwig	`; use userContext to store state`
449	200	hellwig	`debug:`
450	16	hellwig	`.nosyn`
451	201	hellwig	`ldhi $24,userContext`
452			`or $24,$24,userContext`
453			`stw $0,$24,0*4 ; registers`
454			`stw $1,$24,1*4`
455			`stw $2,$24,2*4`
456			`stw $3,$24,3*4`
457			`stw $4,$24,4*4`
458			`stw $5,$24,5*4`
459			`stw $6,$24,6*4`
460			`stw $7,$24,7*4`
461			`stw $8,$24,8*4`
462			`stw $9,$24,9*4`
463			`stw $10,$24,10*4`
464			`stw $11,$24,11*4`
465			`stw $12,$24,12*4`
466			`stw $13,$24,13*4`
467			`stw $14,$24,14*4`
468			`stw $15,$24,15*4`
469			`stw $16,$24,16*4`
470			`stw $17,$24,17*4`
471			`stw $18,$24,18*4`
472			`stw $19,$24,19*4`
473			`stw $20,$24,20*4`
474			`stw $21,$24,21*4`
475			`stw $22,$24,22*4`
476			`stw $23,$24,23*4`
477			`stw $24,$24,24*4`
478			`stw $25,$24,25*4`
479			`stw $26,$24,26*4`
480			`stw $27,$24,27*4`
481			`stw $28,$24,28*4`
482			`stw $29,$24,29*4`
483			`stw $30,$24,30*4`
484			`stw $31,$24,31*4`
485	16	hellwig	`mvfs $8,PSW`
486	201	hellwig	`stw $8,$24,32*4 ; psw`
487	16	hellwig	`mvfs $8,TLB_INDEX`
488	201	hellwig	`stw $8,$24,33*4 ; tlbIndex`
489	16	hellwig	`mvfs $8,TLB_ENTRY_HI`
490	201	hellwig	`stw $8,$24,34*4 ; tlbEntryHi`
491	16	hellwig	`mvfs $8,TLB_ENTRY_LO`
492	201	hellwig	`stw $8,$24,35*4 ; tlbEntryLo`
493	84	hellwig	`mvfs $8,BAD_ADDRESS`
494	201	hellwig	`stw $8,$24,36*4 ; badAddress`
495	180	hellwig	`mvfs $8,BAD_ACCESS`
496	201	hellwig	`stw $8,$24,37*4 ; badAccess`
497	16	hellwig	`.syn`
498			`j loadState`

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