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[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 64

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;
; start.s -- ECO32 ROM monitor startup and support routines
;
 
        .set    dmapaddr,0xC0000000     ; base of directly mapped addresses
        .set    stacktop,0xC0010000     ; monitor stack is at top of 64K
 
        .set    PSW,0                    ; reg # of PSW
        .set    V_SHIFT,27              ; interrupt vector ctrl bit
        .set    V,1 << V_SHIFT
 
        .set    TLB_INDEX,1             ; reg # of TLB Index
        .set    TLB_ENTRY_HI,2          ; reg # of TLB EntryHi
        .set    TLB_ENTRY_LO,3          ; reg # of TLB EntryLo
        .set    TLB_ENTRIES,32          ; number of TLB entries
 
        .set    USER_CONTEXT_SIZE,36*4  ; size of user context
 
        .set    BIO_OUT,0xF1000000      ; board I/O output port
        .set    SPI_EN,0x80000000       ; SPI bus enable ctrl bit
 
;***************************************************************
 
        .import _ecode
        .import _edata
        .import _ebss
 
        .import kbdinit
        .import kbdinchk
        .import kbdin
 
        .import dspinit
        .import dspoutchk
        .import dspout
 
        .import serinit
        .import ser0inchk
        .import ser0in
        .import ser0outchk
        .import ser0out
 
        .import sctcapctl
        .import sctioctl
        .import sctcapser
        .import sctioser
 
        .import main
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export cinchk
        .export cin
        .export coutchk
        .export cout
        .export sinchk
        .export sin
        .export soutchk
        .export sout
        .export dskcap
        .export dskio
 
        .export setISR
        .export setUMSR
        .export isrPtr
        .export umsrPtr
 
        .export getTLB_HI
        .export getTLB_LO
        .export setTLB
 
        .export saveState
        .export monitorReturn
 
        .import userContext
        .export resume
 
;***************************************************************
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
;***************************************************************
 
        .code
        .align  4
 
reset:
        j       start
 
interrupt:
        j       isr
 
userMiss:
        j       umsr
 
;***************************************************************
 
        .code
        .align  4
 
cinchk:
        j       kbdinchk
;       j       ser0inchk
 
cin:
        j       kbdin
;       j       ser0in
 
coutchk:
        j       dspoutchk
;       j       ser0outchk
 
cout:
        j       dspout
;       j       ser0out
 
sinchk:
        j       ser0inchk
 
sin:
        j       ser0in
 
soutchk:
        j       ser0outchk
 
sout:
        j       ser0out
 
dskcap:
        j       dcap
 
dskio:
        j       dio
 
reserved1:
        j       reserved1
 
reserved2:
        j       reserved2
 
reserved3:
        j       reserved3
 
setISR:
        j       setISR1
 
setUMSR:
        j       setUMSR1
 
;***************************************************************
 
        .code
        .align  4
 
start:
        ; let irq/exc vectors point to RAM
        add     $8,$0,V
        mvts    $8,PSW
 
        ; initialize TLB
        mvts    $0,TLB_ENTRY_LO          ; invalidate all TLB entries
        add     $8,$0,dmapaddr           ; by impossible virtual page number
        add     $9,$0,$0
        add     $10,$0,TLB_ENTRIES
tlbloop:
        mvts    $8,TLB_ENTRY_HI
        mvts    $9,TLB_INDEX
        tbwi
        add     $8,$8,0x1000            ; all entries must be different
        add     $9,$9,1
        bne     $9,$10,tlbloop
 
        ; copy data segment
        add     $10,$0,_bdata            ; lowest dst addr to be written to
        add     $8,$0,_edata             ; one above the top dst addr
        sub     $9,$8,$10               ; $9 = size of data segment
        add     $9,$9,_ecode            ; data is waiting right after code
        j       cpytest
cpyloop:
        ldw     $11,$9,0         ; src addr in $9
        stw     $11,$8,0         ; dst addr in $8
cpytest:
        sub     $8,$8,4                 ; downward
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
 
        ; clear bss segment
        add     $8,$0,_bbss              ; start with first word of bss
        add     $9,$0,_ebss              ; this is one above the top
        j       clrtest
clrloop:
        stw     $0,$8,0                   ; dst addr in $8
        add     $8,$8,4                 ; upward
clrtest:
        bltu    $8,$9,clrloop
 
        ; now do some useful work
        add     $29,$0,stacktop          ; setup monitor stack
        jal     dspinit                 ; init display
        jal     kbdinit                 ; init keyboard
        jal     serinit                 ; init serial interface
        jal     main                    ; enter command loop
 
        ; main should never return
        j       start                   ; just to be sure...
 
;***************************************************************
 
        .code
        .align  4
 
        ; Word getTLB_HI(int index)
getTLB_HI:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_HI
        jr      $31
 
        ; Word getTLB_LO(int index)
getTLB_LO:
        mvts    $4,TLB_INDEX
        tbri
        mvfs    $2,TLB_ENTRY_LO
        jr      $31
 
        ; void setTLB(int index, Word entryHi, Word entryLo)
setTLB:
        mvts    $4,TLB_INDEX
        mvts    $5,TLB_ENTRY_HI
        mvts    $6,TLB_ENTRY_LO
        tbwi
        jr      $31
 
;***************************************************************
 
        .code
        .align  4
 
        ; int dskcap(int dskno)
dcap:
        bne     $4,$0,dcapser
        j       sctcapctl
dcapser:
        j       sctcapser
 
        ; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
dio:
        bne     $4,$0,dioser
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioctl
dioser:
        add     $4,$5,$0
        add     $5,$6,$0
        add     $6,$7,$0
        ldw     $7,$29,16
        j       sctioser
 
;***************************************************************
 
        .code
        .align  4
 
        ; void setISR(Word ptr)
setISR1:
        stw     $4,$0,isrPtr
        jr      $31
 
        ; void setUMSR(Word ptr)
setUMSR1:
        stw     $4,$0,umsrPtr
        jr      $31
 
        .data
        .align  4
 
isrPtr:
        .word   0
 
umsrPtr:
        .word   0
 
;***************************************************************
 
        .code
        .align  4
 
        ; Bool saveState(MonitorState *msp)
        ; always return 'true' here
saveState:
        stw     $31,$4,0*4               ; return address
        stw     $29,$4,1*4              ; stack pointer
        stw     $16,$4,2*4              ; local variables
        stw     $17,$4,3*4
        stw     $18,$4,4*4
        stw     $19,$4,5*4
        stw     $20,$4,6*4
        stw     $21,$4,7*4
        stw     $22,$4,8*4
        stw     $23,$4,9*4
        add     $2,$0,1
        jr      $31
 
        ; load state when re-entering monitor
        ; this appears as if returning from saveState
        ; but the return value is 'false' here
loadState:
        ldw     $8,$0,monitorReturn
        beq     $8,$0,loadState          ; fatal error: monitor state lost
        ldw     $31,$8,0*4               ; return address
        ldw     $29,$8,1*4              ; stack pointer
        ldw     $16,$8,2*4              ; local variables
        ldw     $17,$8,3*4
        ldw     $18,$8,4*4
        ldw     $19,$8,5*4
        ldw     $20,$8,6*4
        ldw     $21,$8,7*4
        ldw     $22,$8,8*4
        ldw     $23,$8,9*4
        add     $2,$0,0
        jr      $31
 
        .bss
        .align  4
 
        ; extern MonitorState *monitorReturn
monitorReturn:
        .space  4
 
        ; extern UserContext userContext
userContext:
        .space  USER_CONTEXT_SIZE
 
;***************************************************************
 
        .code
        .align  4
 
        ; void resume(void)
        ; use userContext to load state
resume:
        mvts    $0,PSW
        add     $28,$0,userContext
        .nosyn
        ldw     $8,$28,33*4             ; tlbIndex
        mvts    $8,TLB_INDEX
        ldw     $8,$28,34*4             ; tlbEntryHi
        mvts    $8,TLB_ENTRY_HI
        ldw     $8,$28,35*4             ; tlbEntryLo
        mvts    $8,TLB_ENTRY_LO
        ;ldw    $0,$28,0*4              ; registers
        ldw     $1,$28,1*4
        ldw     $2,$28,2*4
        ldw     $3,$28,3*4
        ldw     $4,$28,4*4
        ldw     $5,$28,5*4
        ldw     $6,$28,6*4
        ldw     $7,$28,7*4
        ldw     $8,$28,8*4
        ldw     $9,$28,9*4
        ldw     $10,$28,10*4
        ldw     $11,$28,11*4
        ldw     $12,$28,12*4
        ldw     $13,$28,13*4
        ldw     $14,$28,14*4
        ldw     $15,$28,15*4
        ldw     $16,$28,16*4
        ldw     $17,$28,17*4
        ldw     $18,$28,18*4
        ldw     $19,$28,19*4
        ldw     $20,$28,20*4
        ldw     $21,$28,21*4
        ldw     $22,$28,22*4
        ldw     $23,$28,23*4
        ldw     $24,$28,24*4
        ldw     $25,$28,25*4
        ldw     $26,$28,26*4
        ldw     $27,$28,27*4
        ;ldw    $28,$28,28*4
        ldw     $29,$28,29*4
        ldw     $30,$28,30*4
        ldw     $31,$28,31*4
        ldw     $28,$28,32*4            ; psw
        mvts    $28,PSW
        rfx
        .syn
 
        ; interrupt entry
        ; use userContext to store state
isr:
umsr:
        .nosyn
        ldhi    $28,userContext
        or      $28,$28,userContext
        stw     $0,$28,0*4                ; registers
        stw     $1,$28,1*4
        stw     $2,$28,2*4
        stw     $3,$28,3*4
        stw     $4,$28,4*4
        stw     $5,$28,5*4
        stw     $6,$28,6*4
        stw     $7,$28,7*4
        stw     $8,$28,8*4
        stw     $9,$28,9*4
        stw     $10,$28,10*4
        stw     $11,$28,11*4
        stw     $12,$28,12*4
        stw     $13,$28,13*4
        stw     $14,$28,14*4
        stw     $15,$28,15*4
        stw     $16,$28,16*4
        stw     $17,$28,17*4
        stw     $18,$28,18*4
        stw     $19,$28,19*4
        stw     $20,$28,20*4
        stw     $21,$28,21*4
        stw     $22,$28,22*4
        stw     $23,$28,23*4
        stw     $24,$28,24*4
        stw     $25,$28,25*4
        stw     $26,$28,26*4
        stw     $27,$28,27*4
        stw     $28,$28,28*4
        stw     $29,$28,29*4
        stw     $30,$28,30*4
        stw     $31,$28,31*4
        mvfs    $8,PSW
        stw     $8,$28,32*4             ; psw
        mvfs    $8,TLB_INDEX
        stw     $8,$28,33*4             ; tlbIndex
        mvfs    $8,TLB_ENTRY_HI
        stw     $8,$28,34*4             ; tlbEntryHi
        mvfs    $8,TLB_ENTRY_LO
        stw     $8,$28,35*4             ; tlbEntryLo
        .syn
        j       loadState

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [monitor/] [monitor/] [boards/] [xsa-xst-3/] [start.s] - Blame information for rev 64

Line No.	Rev	Author	Line
1	16	hellwig	`;`
2			`; start.s -- ECO32 ROM monitor startup and support routines`
3			`;`
4
5			`.set dmapaddr,0xC0000000 ; base of directly mapped addresses`
6	55	hellwig	`.set stacktop,0xC0010000 ; monitor stack is at top of 64K`
7	16	hellwig
8			`.set PSW,0 ; reg # of PSW`
9	55	hellwig	`.set V_SHIFT,27 ; interrupt vector ctrl bit`
10			`.set V,1 << V_SHIFT`
11
12	16	hellwig	`.set TLB_INDEX,1 ; reg # of TLB Index`
13			`.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi`
14			`.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo`
15			`.set TLB_ENTRIES,32 ; number of TLB entries`
16
17			`.set USER_CONTEXT_SIZE,36*4 ; size of user context`
18
19	55	hellwig	`.set BIO_OUT,0xF1000000 ; board I/O output port`
20			`.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit`
21
22	16	hellwig	`;***************************************************************`
23
24			`.import _ecode`
25			`.import _edata`
26			`.import _ebss`
27
28			`.import kbdinit`
29			`.import kbdinchk`
30			`.import kbdin`
31
32			`.import dspinit`
33			`.import dspoutchk`
34			`.import dspout`
35
36			`.import serinit`
37			`.import ser0inchk`
38			`.import ser0in`
39			`.import ser0outchk`
40			`.import ser0out`
41
42			`.import sctcapctl`
43			`.import sctioctl`
44			`.import sctcapser`
45			`.import sctioser`
46
47			`.import main`
48
49			`.export _bcode`
50			`.export _bdata`
51			`.export _bbss`
52
53			`.export cinchk`
54			`.export cin`
55			`.export coutchk`
56			`.export cout`
57			`.export sinchk`
58			`.export sin`
59			`.export soutchk`
60			`.export sout`
61			`.export dskcap`
62			`.export dskio`
63
64	55	hellwig	`.export setISR`
65			`.export setUMSR`
66			`.export isrPtr`
67			`.export umsrPtr`
68
69	16	hellwig	`.export getTLB_HI`
70			`.export getTLB_LO`
71			`.export setTLB`
72
73			`.export saveState`
74			`.export monitorReturn`
75
76			`.import userContext`
77			`.export resume`
78
79			`;***************************************************************`
80
81			`.code`
82			`_bcode:`
83
84			`.data`
85			`_bdata:`
86
87			`.bss`
88			`_bbss:`
89
90			`;***************************************************************`
91
92			`.code`
93			`.align 4`
94
95			`reset:`
96			`j start`
97
98			`interrupt:`
99			`j isr`
100
101			`userMiss:`
102			`j umsr`
103
104			`;***************************************************************`
105
106			`.code`
107			`.align 4`
108
109			`cinchk:`
110	55	hellwig	`j kbdinchk`
111			`; j ser0inchk`
112	16	hellwig
113			`cin:`
114	55	hellwig	`j kbdin`
115			`; j ser0in`
116	16	hellwig
117			`coutchk:`
118	55	hellwig	`j dspoutchk`
119			`; j ser0outchk`
120	16	hellwig
121			`cout:`
122	55	hellwig	`j dspout`
123			`; j ser0out`
124	16	hellwig
125			`sinchk:`
126			`j ser0inchk`
127
128			`sin:`
129			`j ser0in`
130
131			`soutchk:`
132			`j ser0outchk`
133
134			`sout:`
135			`j ser0out`
136
137			`dskcap:`
138			`j dcap`
139
140			`dskio:`
141			`j dio`
142
143	55	hellwig	`reserved1:`
144			`j reserved1`
145
146			`reserved2:`
147			`j reserved2`
148
149			`reserved3:`
150			`j reserved3`
151
152			`setISR:`
153			`j setISR1`
154
155			`setUMSR:`
156			`j setUMSR1`
157
158	16	hellwig	`;***************************************************************`
159
160			`.code`
161			`.align 4`
162
163			`start:`
164	55	hellwig	`; let irq/exc vectors point to RAM`
165			`add $8,$0,V`
166			`mvts $8,PSW`
167	16	hellwig
168			`; initialize TLB`
169			`mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries`
170			`add $8,$0,dmapaddr ; by impossible virtual page number`
171			`add $9,$0,$0`
172			`add $10,$0,TLB_ENTRIES`
173			`tlbloop:`
174			`mvts $8,TLB_ENTRY_HI`
175			`mvts $9,TLB_INDEX`
176			`tbwi`
177			`add $8,$8,0x1000 ; all entries must be different`
178			`add $9,$9,1`
179			`bne $9,$10,tlbloop`
180
181			`; copy data segment`
182			`add $10,$0,_bdata ; lowest dst addr to be written to`
183			`add $8,$0,_edata ; one above the top dst addr`
184			`sub $9,$8,$10 ; $9 = size of data segment`
185			`add $9,$9,_ecode ; data is waiting right after code`
186			`j cpytest`
187			`cpyloop:`
188			`ldw $11,$9,0 ; src addr in $9`
189			`stw $11,$8,0 ; dst addr in $8`
190			`cpytest:`
191			`sub $8,$8,4 ; downward`
192			`sub $9,$9,4`
193			`bgeu $8,$10,cpyloop`
194
195			`; clear bss segment`
196			`add $8,$0,_bbss ; start with first word of bss`
197			`add $9,$0,_ebss ; this is one above the top`
198			`j clrtest`
199			`clrloop:`
200			`stw $0,$8,0 ; dst addr in $8`
201			`add $8,$8,4 ; upward`
202			`clrtest:`
203			`bltu $8,$9,clrloop`
204
205			`; now do some useful work`
206			`add $29,$0,stacktop ; setup monitor stack`
207	55	hellwig	`jal dspinit ; init display`
208			`jal kbdinit ; init keyboard`
209	16	hellwig	`jal serinit ; init serial interface`
210			`jal main ; enter command loop`
211
212			`; main should never return`
213			`j start ; just to be sure...`
214
215			`;***************************************************************`
216
217	55	hellwig	`.code`
218			`.align 4`
219
220	16	hellwig	`; Word getTLB_HI(int index)`
221			`getTLB_HI:`
222			`mvts $4,TLB_INDEX`
223			`tbri`
224			`mvfs $2,TLB_ENTRY_HI`
225			`jr $31`
226
227			`; Word getTLB_LO(int index)`
228			`getTLB_LO:`
229			`mvts $4,TLB_INDEX`
230			`tbri`
231			`mvfs $2,TLB_ENTRY_LO`
232			`jr $31`
233
234			`; void setTLB(int index, Word entryHi, Word entryLo)`
235			`setTLB:`
236			`mvts $4,TLB_INDEX`
237			`mvts $5,TLB_ENTRY_HI`
238			`mvts $6,TLB_ENTRY_LO`
239			`tbwi`
240			`jr $31`
241
242			`;***************************************************************`
243
244	55	hellwig	`.code`
245			`.align 4`
246
247	16	hellwig	`; int dskcap(int dskno)`
248			`dcap:`
249			`bne $4,$0,dcapser`
250			`j sctcapctl`
251			`dcapser:`
252			`j sctcapser`
253
254			`; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)`
255			`dio:`
256			`bne $4,$0,dioser`
257			`add $4,$5,$0`
258			`add $5,$6,$0`
259			`add $6,$7,$0`
260			`ldw $7,$29,16`
261			`j sctioctl`
262			`dioser:`
263			`add $4,$5,$0`
264			`add $5,$6,$0`
265			`add $6,$7,$0`
266			`ldw $7,$29,16`
267			`j sctioser`
268
269			`;***************************************************************`
270
271			`.code`
272			`.align 4`
273
274	55	hellwig	`; void setISR(Word ptr)`
275			`setISR1:`
276			`stw $4,$0,isrPtr`
277			`jr $31`
278
279			`; void setUMSR(Word ptr)`
280			`setUMSR1:`
281			`stw $4,$0,umsrPtr`
282			`jr $31`
283
284			`.data`
285			`.align 4`
286
287			`isrPtr:`
288			`.word 0`
289
290			`umsrPtr:`
291			`.word 0`
292
293			`;***************************************************************`
294
295			`.code`
296			`.align 4`
297
298	16	hellwig	`; Bool saveState(MonitorState *msp)`
299			`; always return 'true' here`
300			`saveState:`
301			`stw $31,$4,0*4 ; return address`
302			`stw $29,$4,1*4 ; stack pointer`
303			`stw $16,$4,2*4 ; local variables`
304			`stw $17,$4,3*4`
305			`stw $18,$4,4*4`
306			`stw $19,$4,5*4`
307			`stw $20,$4,6*4`
308			`stw $21,$4,7*4`
309			`stw $22,$4,8*4`
310			`stw $23,$4,9*4`
311			`add $2,$0,1`
312			`jr $31`
313
314			`; load state when re-entering monitor`
315			`; this appears as if returning from saveState`
316			`; but the return value is 'false' here`
317			`loadState:`
318			`ldw $8,$0,monitorReturn`
319			`beq $8,$0,loadState ; fatal error: monitor state lost`
320			`ldw $31,$8,0*4 ; return address`
321			`ldw $29,$8,1*4 ; stack pointer`
322			`ldw $16,$8,2*4 ; local variables`
323			`ldw $17,$8,3*4`
324			`ldw $18,$8,4*4`
325			`ldw $19,$8,5*4`
326			`ldw $20,$8,6*4`
327			`ldw $21,$8,7*4`
328			`ldw $22,$8,8*4`
329			`ldw $23,$8,9*4`
330			`add $2,$0,0`
331			`jr $31`
332
333			`.bss`
334			`.align 4`
335
336			`; extern MonitorState *monitorReturn`
337			`monitorReturn:`
338			`.space 4`
339
340			`; extern UserContext userContext`
341			`userContext:`
342			`.space USER_CONTEXT_SIZE`
343
344			`;***************************************************************`
345
346			`.code`
347			`.align 4`
348
349			`; void resume(void)`
350			`; use userContext to load state`
351			`resume:`
352			`mvts $0,PSW`
353			`add $28,$0,userContext`
354			`.nosyn`
355			`ldw $8,$28,33*4 ; tlbIndex`
356			`mvts $8,TLB_INDEX`
357	55	hellwig	`ldw $8,$28,34*4 ; tlbEntryHi`
358	16	hellwig	`mvts $8,TLB_ENTRY_HI`
359			`ldw $8,$28,35*4 ; tlbEntryLo`
360			`mvts $8,TLB_ENTRY_LO`
361			`;ldw $0,$28,0*4 ; registers`
362			`ldw $1,$28,1*4`
363			`ldw $2,$28,2*4`
364			`ldw $3,$28,3*4`
365			`ldw $4,$28,4*4`
366			`ldw $5,$28,5*4`
367			`ldw $6,$28,6*4`
368			`ldw $7,$28,7*4`
369			`ldw $8,$28,8*4`
370			`ldw $9,$28,9*4`
371			`ldw $10,$28,10*4`
372			`ldw $11,$28,11*4`
373			`ldw $12,$28,12*4`
374			`ldw $13,$28,13*4`
375			`ldw $14,$28,14*4`
376			`ldw $15,$28,15*4`
377			`ldw $16,$28,16*4`
378			`ldw $17,$28,17*4`
379			`ldw $18,$28,18*4`
380			`ldw $19,$28,19*4`
381			`ldw $20,$28,20*4`
382			`ldw $21,$28,21*4`
383			`ldw $22,$28,22*4`
384			`ldw $23,$28,23*4`
385			`ldw $24,$28,24*4`
386			`ldw $25,$28,25*4`
387			`ldw $26,$28,26*4`
388			`ldw $27,$28,27*4`
389			`;ldw $28,$28,28*4`
390			`ldw $29,$28,29*4`
391			`ldw $30,$28,30*4`
392			`ldw $31,$28,31*4`
393			`ldw $28,$28,32*4 ; psw`
394			`mvts $28,PSW`
395			`rfx`
396			`.syn`
397
398			`; interrupt entry`
399			`; use userContext to store state`
400			`isr:`
401			`umsr:`
402			`.nosyn`
403			`ldhi $28,userContext`
404			`or $28,$28,userContext`
405			`stw $0,$28,0*4 ; registers`
406			`stw $1,$28,1*4`
407			`stw $2,$28,2*4`
408			`stw $3,$28,3*4`
409			`stw $4,$28,4*4`
410			`stw $5,$28,5*4`
411			`stw $6,$28,6*4`
412			`stw $7,$28,7*4`
413			`stw $8,$28,8*4`
414			`stw $9,$28,9*4`
415			`stw $10,$28,10*4`
416			`stw $11,$28,11*4`
417			`stw $12,$28,12*4`
418			`stw $13,$28,13*4`
419			`stw $14,$28,14*4`
420			`stw $15,$28,15*4`
421			`stw $16,$28,16*4`
422			`stw $17,$28,17*4`
423			`stw $18,$28,18*4`
424			`stw $19,$28,19*4`
425			`stw $20,$28,20*4`
426			`stw $21,$28,21*4`
427			`stw $22,$28,22*4`
428			`stw $23,$28,23*4`
429			`stw $24,$28,24*4`
430			`stw $25,$28,25*4`
431			`stw $26,$28,26*4`
432			`stw $27,$28,27*4`
433			`stw $28,$28,28*4`
434			`stw $29,$28,29*4`
435			`stw $30,$28,30*4`
436			`stw $31,$28,31*4`
437			`mvfs $8,PSW`
438			`stw $8,$28,32*4 ; psw`
439			`mvfs $8,TLB_INDEX`
440			`stw $8,$28,33*4 ; tlbIndex`
441			`mvfs $8,TLB_ENTRY_HI`
442			`stw $8,$28,34*4 ; tlbEntryHi`
443			`mvfs $8,TLB_ENTRY_LO`
444			`stw $8,$28,35*4 ; tlbEntryLo`
445			`.syn`
446			`j loadState`