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[/] [eco32/] [trunk/] [monitor/] [monitor/] [common/] [cpu.c] - Blame information for rev 112

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/*
 * cpu.c -- execute instructions
 */
 
 
#include "common.h"
#include "stdarg.h"
#include "romlib.h"
#include "instr.h"
#include "cpu.h"
#include "mmu.h"
#include "start.h"
 
 
#define RR(n)           r[n]
#define WR(n,d)         ((void) ((n) != 0 ? r[n] = (d) : (d)))
 
#define BREAK           (OP_TRAP << 26)
 
 
/**************************************************************/
 
 
static Word pc;                 /* program counter */
static Word psw;                /* processor status word */
static Word r[32];              /* general purpose registers */
 
static Bool breakSet;           /* breakpoint set if true */
static Word breakAddr;          /* if breakSet, this is where */
 
 
/**************************************************************/
 
 
Word cpuGetPC(void) {
  return pc;
}
 
 
void cpuSetPC(Word addr) {
  pc = addr;
}
 
 
Word cpuGetReg(int regnum) {
  return RR(regnum & 0x1F);
}
 
 
void cpuSetReg(int regnum, Word value) {
  WR(regnum & 0x1F, value);
}
 
 
Word cpuGetPSW(void) {
  return psw;
}
 
 
void cpuSetPSW(Word value) {
  psw = value;
}
 
 
Bool cpuTestBreak(void) {
  return breakSet;
}
 
 
Word cpuGetBreak(void) {
  return breakAddr;
}
 
 
void cpuSetBreak(Word addr) {
  breakAddr = addr;
  breakSet = true;
}
 
 
void cpuResetBreak(void) {
  breakSet = false;
}
 
 
/**************************************************************/
 
 
static char *cause[32] = {
  /*  0 */  "serial line 0 xmt interrupt",
  /*  1 */  "serial line 0 rcv interrupt",
  /*  2 */  "serial line 1 xmt interrupt",
  /*  3 */  "serial line 1 rcv interrupt",
  /*  4 */  "keyboard interrupt",
  /*  5 */  "unknown interrupt",
  /*  6 */  "unknown interrupt",
  /*  7 */  "unknown interrupt",
  /*  8 */  "disk interrupt",
  /*  9 */  "unknown interrupt",
  /* 10 */  "unknown interrupt",
  /* 11 */  "unknown interrupt",
  /* 12 */  "unknown interrupt",
  /* 13 */  "unknown interrupt",
  /* 14 */  "timer 0 interrupt",
  /* 15 */  "timer 1 interrupt",
  /* 16 */  "bus timeout exception",
  /* 17 */  "illegal instruction exception",
  /* 18 */  "privileged instruction exception",
  /* 19 */  "divide instruction exception",
  /* 20 */  "trap instruction exception",
  /* 21 */  "TLB miss exception",
  /* 22 */  "TLB write exception",
  /* 23 */  "TLB invalid exception",
  /* 24 */  "illegal address exception",
  /* 25 */  "privileged address exception",
  /* 26 */  "unknown exception",
  /* 27 */  "unknown exception",
  /* 28 */  "unknown exception",
  /* 29 */  "unknown exception",
  /* 30 */  "unknown exception",
  /* 31 */  "unknown exception"
};
 
 
char *exceptionToString(int exception) {
  if (exception < 0 ||
      exception >= sizeof(cause)/sizeof(cause[0])) {
    return "<exception number out of bounds>";
  }
  return cause[exception];
}
 
 
/**************************************************************/
 
 
static Byte stepType[64] = {
  /*          0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  */
  /* 0x00 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  /* 0x10 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  /* 0x20 */  2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 4, 3, 4, 1, 0,
  /* 0x30 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
 
 
static Bool evalCond(int cc, Word a, Word b) {
  switch (cc) {
    case 0:
      /* equal */
      if (a == b) {
        return true;
      }
      break;
    case 1:
      /* not equal */
      if (a != b) {
        return true;
      }
      break;
    case 2:
      /* less or equal (signed) */
      if ((signed int) a <= (signed int) b) {
        return true;
      }
      break;
    case 3:
      /* less or equal (unsigned) */
      if (a <= b) {
        return true;
      }
      break;
    case 4:
      /* less than (signed) */
      if ((signed int) a < (signed int) b) {
        return true;
      }
      break;
    case 5:
      /* less than (unsigned) */
      if (a < b) {
        return true;
      }
      break;
    case 6:
      /* greater or equal (signed) */
      if ((signed int) a >= (signed int) b) {
        return true;
      }
      break;
    case 7:
      /* greater or equal (unsigned) */
      if (a >= b) {
        return true;
      }
      break;
    case 8:
      /* greater than (signed) */
      if ((signed int) a > (signed int) b) {
        return true;
      }
      break;
    case 9:
      /* greater than (unsigned) */
      if (a > b) {
        return true;
      }
      break;
    default:
      /* this should never happen */
      printf("cannot compute condition code %d\n", cc);
      break;
  }
  return false;
}
 
 
void cpuStep(void) {
  Word instr;
  int opcode;
  int reg1, reg2;
  Half immed;
  Word offset;
  Word nextAddr;
  Word nextInstr;
  int i;
  MonitorState stepState;
  MonitorState *origReturn;
 
  instr = mmuReadWord(pc);
  opcode = (instr >> 26) & 0x3F;
  reg1 = (instr >> 21) & 0x1F;
  reg2 = (instr >> 16) & 0x1F;
  immed = instr & 0x0000FFFF;
  offset = instr & 0x03FFFFFF;
  switch (stepType[opcode]) {
    case 1:
      /* next instruction follows current one immediately */
      nextAddr = pc + 4;
      break;
    case 2:
      /* next instruction conditionally reached by PC relative branch */
      nextAddr = pc + 4;
      if (evalCond(opcode - OP_BEQ, RR(reg1), RR(reg2))) {
        nextAddr += SEXT16(immed) << 2;
      }
      break;
    case 3:
      /* next instruction reached by PC relative jump */
      nextAddr = pc + 4 + (SEXT26(offset) << 2);
      break;
    case 4:
      /* next instruction reached by jump to register contents */
      nextAddr = RR(reg1) & 0xFFFFFFFC;
      break;
    default:
      printf("cannot single-step instruction with opcode 0x%02X\n",
             opcode);
      return;
  }
  nextInstr = mmuReadWord(nextAddr);
  mmuWriteWord(nextAddr, BREAK);
  for (i = 0; i < 32; i++) {
    userContext.reg[i] = RR(i);
  }
  userContext.reg[30] = pc;
  userContext.psw = psw;
  userContext.tlbIndex = mmuGetIndex();
  userContext.tlbHi = mmuGetEntryHi();
  userContext.tlbLo = mmuGetEntryLo();
  userContext.badAddr = mmuGetBadAddr();
  if (saveState(&stepState)) {
    origReturn = monitorReturn;
    monitorReturn = &stepState;
    resume();
  }
  monitorReturn = origReturn;
  for (i = 0; i < 32; i++) {
    WR(i, userContext.reg[i]);
  }
  pc = userContext.reg[30];
  psw = userContext.psw;
  mmuSetIndex(userContext.tlbIndex);
  mmuSetEntryHi(userContext.tlbHi);
  mmuSetEntryLo(userContext.tlbLo);
  mmuSetBadAddr(userContext.badAddr);
  mmuWriteWord(nextAddr, nextInstr);
  if (nextAddr == pc) {
    return;
  }
  if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
      (mmuGetEntryHi() & 0x80000000) == 0) {
    /* TLB user miss */
    if (umsrPtr == 0x00000000) {
      printf("unexpected TLB user miss exception occurred\n");
      return;
    }
    pc = umsrPtr;
  } else {
    /* any other exception */
    if (isrPtr == 0x00000000) {
      printf("unexpected %s occurred\n",
             exceptionToString((psw & PSW_PRIO_MASK) >> 16));
      return;
    }
    pc = isrPtr;
  }
}
 
 
void cpuRun(void) {
  Word instr;
  int i;
  MonitorState runState;
  MonitorState *origReturn;
 
  if (breakSet && breakAddr == pc) {
    /* single-step one instruction */
    cpuStep();
  }
  while (1) {
    if (breakSet) {
      instr = mmuReadWord(breakAddr);
      mmuWriteWord(breakAddr, BREAK);
    }
    for (i = 0; i < 32; i++) {
      userContext.reg[i] = RR(i);
    }
    userContext.reg[30] = pc;
    userContext.psw = psw;
    userContext.tlbIndex = mmuGetIndex();
    userContext.tlbHi = mmuGetEntryHi();
    userContext.tlbLo = mmuGetEntryLo();
    userContext.badAddr = mmuGetBadAddr();
    if (saveState(&runState)) {
      origReturn = monitorReturn;
      monitorReturn = &runState;
      resume();
    }
    monitorReturn = origReturn;
    for (i = 0; i < 32; i++) {
      WR(i, userContext.reg[i]);
    }
    pc = userContext.reg[30];
    psw = userContext.psw;
    mmuSetIndex(userContext.tlbIndex);
    mmuSetEntryHi(userContext.tlbHi);
    mmuSetEntryLo(userContext.tlbLo);
    mmuSetBadAddr(userContext.badAddr);
    if (breakSet) {
      mmuWriteWord(breakAddr, instr);
    }
    if (breakSet && breakAddr == pc) {
      return;
    }
    if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
        (mmuGetEntryHi() & 0x80000000) == 0) {
      /* TLB user miss */
      if (umsrPtr == 0x00000000) {
        printf("unexpected TLB user miss exception occurred\n");
        return;
      }
      pc = umsrPtr;
    } else {
      /* any other exception */
      if (isrPtr == 0x00000000) {
        printf("unexpected %s occurred\n",
               exceptionToString((psw & PSW_PRIO_MASK) >> 16));
        return;
      }
      pc = isrPtr;
    }
  }
}

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [monitor/] [monitor/] [common/] [cpu.c] - Blame information for rev 112

Line No.	Rev	Author	Line
1	59	hellwig	`/*`
2			`* cpu.c -- execute instructions`
3			`*/`
4
5
6			`#include "common.h"`
7			`#include "stdarg.h"`
8			`#include "romlib.h"`
9			`#include "instr.h"`
10			`#include "cpu.h"`
11			`#include "mmu.h"`
12			`#include "start.h"`
13
14
15			`#define RR(n) r[n]`
16			`#define WR(n,d) ((void) ((n) != 0 ? r[n] = (d) : (d)))`
17
18			`#define BREAK (OP_TRAP << 26)`
19
20
21			`/**************************************************************/`
22
23
24			`static Word pc; /* program counter */`
25			`static Word psw; /* processor status word */`
26			`static Word r[32]; /* general purpose registers */`
27
28			`static Bool breakSet; /* breakpoint set if true */`
29			`static Word breakAddr; /* if breakSet, this is where */`
30
31
32			`/**************************************************************/`
33
34
35			`Word cpuGetPC(void) {`
36			`return pc;`
37			`}`
38
39
40			`void cpuSetPC(Word addr) {`
41			`pc = addr;`
42			`}`
43
44
45			`Word cpuGetReg(int regnum) {`
46			`return RR(regnum & 0x1F);`
47			`}`
48
49
50			`void cpuSetReg(int regnum, Word value) {`
51			`WR(regnum & 0x1F, value);`
52			`}`
53
54
55			`Word cpuGetPSW(void) {`
56			`return psw;`
57			`}`
58
59
60			`void cpuSetPSW(Word value) {`
61			`psw = value;`
62			`}`
63
64
65			`Bool cpuTestBreak(void) {`
66			`return breakSet;`
67			`}`
68
69
70			`Word cpuGetBreak(void) {`
71			`return breakAddr;`
72			`}`
73
74
75			`void cpuSetBreak(Word addr) {`
76			`breakAddr = addr;`
77			`breakSet = true;`
78			`}`
79
80
81			`void cpuResetBreak(void) {`
82			`breakSet = false;`
83			`}`
84
85
86			`/**************************************************************/`
87
88
89			`static char *cause[32] = {`
90			`/* 0 */ "serial line 0 xmt interrupt",`
91			`/* 1 */ "serial line 0 rcv interrupt",`
92			`/* 2 */ "serial line 1 xmt interrupt",`
93			`/* 3 */ "serial line 1 rcv interrupt",`
94			`/* 4 */ "keyboard interrupt",`
95			`/* 5 */ "unknown interrupt",`
96			`/* 6 */ "unknown interrupt",`
97			`/* 7 */ "unknown interrupt",`
98			`/* 8 */ "disk interrupt",`
99			`/* 9 */ "unknown interrupt",`
100			`/* 10 */ "unknown interrupt",`
101			`/* 11 */ "unknown interrupt",`
102			`/* 12 */ "unknown interrupt",`
103			`/* 13 */ "unknown interrupt",`
104			`/* 14 */ "timer 0 interrupt",`
105			`/* 15 */ "timer 1 interrupt",`
106			`/* 16 */ "bus timeout exception",`
107			`/* 17 */ "illegal instruction exception",`
108			`/* 18 */ "privileged instruction exception",`
109			`/* 19 */ "divide instruction exception",`
110			`/* 20 */ "trap instruction exception",`
111			`/* 21 */ "TLB miss exception",`
112			`/* 22 */ "TLB write exception",`
113			`/* 23 */ "TLB invalid exception",`
114			`/* 24 */ "illegal address exception",`
115			`/* 25 */ "privileged address exception",`
116			`/* 26 */ "unknown exception",`
117			`/* 27 */ "unknown exception",`
118			`/* 28 */ "unknown exception",`
119			`/* 29 */ "unknown exception",`
120			`/* 30 */ "unknown exception",`
121			`/* 31 */ "unknown exception"`
122			`};`
123
124
125			`char *exceptionToString(int exception) {`
126			`if (exception < 0 \|\|`
127			`exception >= sizeof(cause)/sizeof(cause[0])) {`
128			`return "<exception number out of bounds>";`
129			`}`
130			`return cause[exception];`
131			`}`
132
133
134			`/**************************************************************/`
135
136
137			`static Byte stepType[64] = {`
138			`/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */`
139			`/* 0x00 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,`
140			`/* 0x10 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,`
141			`/* 0x20 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 4, 3, 4, 1, 0,`
142			`/* 0x30 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,`
143			`};`
144
145
146			`static Bool evalCond(int cc, Word a, Word b) {`
147			`switch (cc) {`
148			`case 0:`
149			`/* equal */`
150			`if (a == b) {`
151			`return true;`
152			`}`
153			`break;`
154			`case 1:`
155			`/* not equal */`
156			`if (a != b) {`
157			`return true;`
158			`}`
159			`break;`
160			`case 2:`
161			`/* less or equal (signed) */`
162			`if ((signed int) a <= (signed int) b) {`
163			`return true;`
164			`}`
165			`break;`
166			`case 3:`
167			`/* less or equal (unsigned) */`
168			`if (a <= b) {`
169			`return true;`
170			`}`
171			`break;`
172			`case 4:`
173			`/* less than (signed) */`
174			`if ((signed int) a < (signed int) b) {`
175			`return true;`
176			`}`
177			`break;`
178			`case 5:`
179			`/* less than (unsigned) */`
180			`if (a < b) {`
181			`return true;`
182			`}`
183			`break;`
184			`case 6:`
185			`/* greater or equal (signed) */`
186			`if ((signed int) a >= (signed int) b) {`
187			`return true;`
188			`}`
189			`break;`
190			`case 7:`
191			`/* greater or equal (unsigned) */`
192			`if (a >= b) {`
193			`return true;`
194			`}`
195			`break;`
196			`case 8:`
197			`/* greater than (signed) */`
198			`if ((signed int) a > (signed int) b) {`
199			`return true;`
200			`}`
201			`break;`
202			`case 9:`
203			`/* greater than (unsigned) */`
204			`if (a > b) {`
205			`return true;`
206			`}`
207			`break;`
208			`default:`
209			`/* this should never happen */`
210			`printf("cannot compute condition code %d\n", cc);`
211			`break;`
212			`}`
213			`return false;`
214			`}`
215
216
217			`void cpuStep(void) {`
218			`Word instr;`
219			`int opcode;`
220			`int reg1, reg2;`
221			`Half immed;`
222			`Word offset;`
223			`Word nextAddr;`
224			`Word nextInstr;`
225			`int i;`
226			`MonitorState stepState;`
227			`MonitorState *origReturn;`
228
229			`instr = mmuReadWord(pc);`
230			`opcode = (instr >> 26) & 0x3F;`
231			`reg1 = (instr >> 21) & 0x1F;`
232			`reg2 = (instr >> 16) & 0x1F;`
233			`immed = instr & 0x0000FFFF;`
234			`offset = instr & 0x03FFFFFF;`
235			`switch (stepType[opcode]) {`
236			`case 1:`
237			`/* next instruction follows current one immediately */`
238			`nextAddr = pc + 4;`
239			`break;`
240			`case 2:`
241			`/* next instruction conditionally reached by PC relative branch */`
242			`nextAddr = pc + 4;`
243			`if (evalCond(opcode - OP_BEQ, RR(reg1), RR(reg2))) {`
244			`nextAddr += SEXT16(immed) << 2;`
245			`}`
246			`break;`
247			`case 3:`
248			`/* next instruction reached by PC relative jump */`
249			`nextAddr = pc + 4 + (SEXT26(offset) << 2);`
250			`break;`
251			`case 4:`
252			`/* next instruction reached by jump to register contents */`
253			`nextAddr = RR(reg1) & 0xFFFFFFFC;`
254			`break;`
255			`default:`
256			`printf("cannot single-step instruction with opcode 0x%02X\n",`
257			`opcode);`
258			`return;`
259			`}`
260			`nextInstr = mmuReadWord(nextAddr);`
261			`mmuWriteWord(nextAddr, BREAK);`
262			`for (i = 0; i < 32; i++) {`
263			`userContext.reg[i] = RR(i);`
264			`}`
265			`userContext.reg[30] = pc;`
266			`userContext.psw = psw;`
267			`userContext.tlbIndex = mmuGetIndex();`
268			`userContext.tlbHi = mmuGetEntryHi();`
269			`userContext.tlbLo = mmuGetEntryLo();`
270	84	hellwig	`userContext.badAddr = mmuGetBadAddr();`
271	59	hellwig	`if (saveState(&stepState)) {`
272			`origReturn = monitorReturn;`
273			`monitorReturn = &stepState;`
274			`resume();`
275			`}`
276			`monitorReturn = origReturn;`
277			`for (i = 0; i < 32; i++) {`
278			`WR(i, userContext.reg[i]);`
279			`}`
280			`pc = userContext.reg[30];`
281			`psw = userContext.psw;`
282			`mmuSetIndex(userContext.tlbIndex);`
283			`mmuSetEntryHi(userContext.tlbHi);`
284			`mmuSetEntryLo(userContext.tlbLo);`
285	84	hellwig	`mmuSetBadAddr(userContext.badAddr);`
286	59	hellwig	`mmuWriteWord(nextAddr, nextInstr);`
287			`if (nextAddr == pc) {`
288			`return;`
289			`}`
290			`if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&`
291			`(mmuGetEntryHi() & 0x80000000) == 0) {`
292			`/* TLB user miss */`
293			`if (umsrPtr == 0x00000000) {`
294			`printf("unexpected TLB user miss exception occurred\n");`
295			`return;`
296			`}`
297			`pc = umsrPtr;`
298			`} else {`
299			`/* any other exception */`
300			`if (isrPtr == 0x00000000) {`
301			`printf("unexpected %s occurred\n",`
302			`exceptionToString((psw & PSW_PRIO_MASK) >> 16));`
303			`return;`
304			`}`
305			`pc = isrPtr;`
306			`}`
307			`}`
308
309
310			`void cpuRun(void) {`
311			`Word instr;`
312			`int i;`
313			`MonitorState runState;`
314			`MonitorState *origReturn;`
315
316			`if (breakSet && breakAddr == pc) {`
317			`/* single-step one instruction */`
318			`cpuStep();`
319			`}`
320			`while (1) {`
321			`if (breakSet) {`
322			`instr = mmuReadWord(breakAddr);`
323			`mmuWriteWord(breakAddr, BREAK);`
324			`}`
325			`for (i = 0; i < 32; i++) {`
326			`userContext.reg[i] = RR(i);`
327			`}`
328			`userContext.reg[30] = pc;`
329			`userContext.psw = psw;`
330			`userContext.tlbIndex = mmuGetIndex();`
331			`userContext.tlbHi = mmuGetEntryHi();`
332			`userContext.tlbLo = mmuGetEntryLo();`
333	84	hellwig	`userContext.badAddr = mmuGetBadAddr();`
334	59	hellwig	`if (saveState(&runState)) {`
335			`origReturn = monitorReturn;`
336			`monitorReturn = &runState;`
337			`resume();`
338			`}`
339			`monitorReturn = origReturn;`
340			`for (i = 0; i < 32; i++) {`
341			`WR(i, userContext.reg[i]);`
342			`}`
343			`pc = userContext.reg[30];`
344			`psw = userContext.psw;`
345			`mmuSetIndex(userContext.tlbIndex);`
346			`mmuSetEntryHi(userContext.tlbHi);`
347			`mmuSetEntryLo(userContext.tlbLo);`
348	84	hellwig	`mmuSetBadAddr(userContext.badAddr);`
349	59	hellwig	`if (breakSet) {`
350			`mmuWriteWord(breakAddr, instr);`
351			`}`
352			`if (breakSet && breakAddr == pc) {`
353			`return;`
354			`}`
355			`if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&`
356			`(mmuGetEntryHi() & 0x80000000) == 0) {`
357			`/* TLB user miss */`
358			`if (umsrPtr == 0x00000000) {`
359			`printf("unexpected TLB user miss exception occurred\n");`
360			`return;`
361			`}`
362			`pc = umsrPtr;`
363			`} else {`
364			`/* any other exception */`
365			`if (isrPtr == 0x00000000) {`
366			`printf("unexpected %s occurred\n",`
367			`exceptionToString((psw & PSW_PRIO_MASK) >> 16));`
368			`return;`
369			`}`
370			`pc = isrPtr;`
371			`}`
372			`}`
373			`}`