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[/] [eco32/] [trunk/] [monitor/] [monitor/] [common/] [cpu.c] - Blame information for rev 128

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Line No. Rev Author Line
1 59 hellwig
/*
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 * cpu.c -- execute instructions
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 */
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#include "common.h"
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#include "stdarg.h"
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#include "romlib.h"
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#include "instr.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "start.h"
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#define RR(n)           r[n]
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#define WR(n,d)         ((void) ((n) != 0 ? r[n] = (d) : (d)))
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#define BREAK           (OP_TRAP << 26)
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/**************************************************************/
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static Word pc;                 /* program counter */
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static Word psw;                /* processor status word */
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static Word r[32];              /* general purpose registers */
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static Bool breakSet;           /* breakpoint set if true */
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static Word breakAddr;          /* if breakSet, this is where */
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/**************************************************************/
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Word cpuGetPC(void) {
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  return pc;
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}
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void cpuSetPC(Word addr) {
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  pc = addr;
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}
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Word cpuGetReg(int regnum) {
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  return RR(regnum & 0x1F);
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}
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void cpuSetReg(int regnum, Word value) {
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  WR(regnum & 0x1F, value);
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}
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Word cpuGetPSW(void) {
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  return psw;
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}
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void cpuSetPSW(Word value) {
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  psw = value;
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}
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Bool cpuTestBreak(void) {
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  return breakSet;
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}
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Word cpuGetBreak(void) {
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  return breakAddr;
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}
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void cpuSetBreak(Word addr) {
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  breakAddr = addr;
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  breakSet = true;
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}
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void cpuResetBreak(void) {
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  breakSet = false;
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}
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/**************************************************************/
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static char *cause[32] = {
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  /*  0 */  "serial line 0 xmt interrupt",
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  /*  1 */  "serial line 0 rcv interrupt",
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  /*  2 */  "serial line 1 xmt interrupt",
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  /*  3 */  "serial line 1 rcv interrupt",
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  /*  4 */  "keyboard interrupt",
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  /*  5 */  "unknown interrupt",
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  /*  6 */  "unknown interrupt",
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  /*  7 */  "unknown interrupt",
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  /*  8 */  "disk interrupt",
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  /*  9 */  "unknown interrupt",
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  /* 10 */  "unknown interrupt",
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  /* 11 */  "unknown interrupt",
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  /* 12 */  "unknown interrupt",
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  /* 13 */  "unknown interrupt",
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  /* 14 */  "timer 0 interrupt",
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  /* 15 */  "timer 1 interrupt",
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  /* 16 */  "bus timeout exception",
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  /* 17 */  "illegal instruction exception",
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  /* 18 */  "privileged instruction exception",
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  /* 19 */  "divide instruction exception",
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  /* 20 */  "trap instruction exception",
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  /* 21 */  "TLB miss exception",
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  /* 22 */  "TLB write exception",
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  /* 23 */  "TLB invalid exception",
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  /* 24 */  "illegal address exception",
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  /* 25 */  "privileged address exception",
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  /* 26 */  "unknown exception",
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  /* 27 */  "unknown exception",
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  /* 28 */  "unknown exception",
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  /* 29 */  "unknown exception",
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  /* 30 */  "unknown exception",
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  /* 31 */  "unknown exception"
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};
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char *exceptionToString(int exception) {
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  if (exception < 0 ||
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      exception >= sizeof(cause)/sizeof(cause[0])) {
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    return "<exception number out of bounds>";
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  }
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  return cause[exception];
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}
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/**************************************************************/
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static Byte stepType[64] = {
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  /*          0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  */
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  /* 0x00 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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  /* 0x10 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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  /* 0x20 */  2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 4, 3, 4, 1, 0,
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  /* 0x30 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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};
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static Bool evalCond(int cc, Word a, Word b) {
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  switch (cc) {
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    case 0:
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      /* equal */
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      if (a == b) {
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        return true;
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      }
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      break;
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    case 1:
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      /* not equal */
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      if (a != b) {
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        return true;
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      }
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      break;
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    case 2:
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      /* less or equal (signed) */
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      if ((signed int) a <= (signed int) b) {
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        return true;
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      }
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      break;
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    case 3:
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      /* less or equal (unsigned) */
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      if (a <= b) {
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        return true;
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      }
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      break;
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    case 4:
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      /* less than (signed) */
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      if ((signed int) a < (signed int) b) {
175
        return true;
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      }
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      break;
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    case 5:
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      /* less than (unsigned) */
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      if (a < b) {
181
        return true;
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      }
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      break;
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    case 6:
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      /* greater or equal (signed) */
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      if ((signed int) a >= (signed int) b) {
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        return true;
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      }
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      break;
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    case 7:
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      /* greater or equal (unsigned) */
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      if (a >= b) {
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        return true;
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      }
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      break;
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    case 8:
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      /* greater than (signed) */
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      if ((signed int) a > (signed int) b) {
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        return true;
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      }
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      break;
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    case 9:
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      /* greater than (unsigned) */
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      if (a > b) {
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        return true;
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      }
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      break;
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    default:
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      /* this should never happen */
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      printf("cannot compute condition code %d\n", cc);
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      break;
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  }
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  return false;
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}
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217
void cpuStep(void) {
218
  Word instr;
219
  int opcode;
220
  int reg1, reg2;
221
  Half immed;
222
  Word offset;
223
  Word nextAddr;
224
  Word nextInstr;
225
  int i;
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  MonitorState stepState;
227
  MonitorState *origReturn;
228
 
229
  instr = mmuReadWord(pc);
230
  opcode = (instr >> 26) & 0x3F;
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  reg1 = (instr >> 21) & 0x1F;
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  reg2 = (instr >> 16) & 0x1F;
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  immed = instr & 0x0000FFFF;
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  offset = instr & 0x03FFFFFF;
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  switch (stepType[opcode]) {
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    case 1:
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      /* next instruction follows current one immediately */
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      nextAddr = pc + 4;
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      break;
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    case 2:
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      /* next instruction conditionally reached by PC relative branch */
242
      nextAddr = pc + 4;
243
      if (evalCond(opcode - OP_BEQ, RR(reg1), RR(reg2))) {
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        nextAddr += SEXT16(immed) << 2;
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      }
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      break;
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    case 3:
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      /* next instruction reached by PC relative jump */
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      nextAddr = pc + 4 + (SEXT26(offset) << 2);
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      break;
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    case 4:
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      /* next instruction reached by jump to register contents */
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      nextAddr = RR(reg1) & 0xFFFFFFFC;
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      break;
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    default:
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      printf("cannot single-step instruction with opcode 0x%02X\n",
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             opcode);
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      return;
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  }
260
  nextInstr = mmuReadWord(nextAddr);
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  mmuWriteWord(nextAddr, BREAK);
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  for (i = 0; i < 32; i++) {
263
    userContext.reg[i] = RR(i);
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  }
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  userContext.reg[30] = pc;
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  userContext.psw = psw;
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  userContext.tlbIndex = mmuGetIndex();
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  userContext.tlbHi = mmuGetEntryHi();
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  userContext.tlbLo = mmuGetEntryLo();
270 84 hellwig
  userContext.badAddr = mmuGetBadAddr();
271 59 hellwig
  if (saveState(&stepState)) {
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    origReturn = monitorReturn;
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    monitorReturn = &stepState;
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    resume();
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  }
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  monitorReturn = origReturn;
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  for (i = 0; i < 32; i++) {
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    WR(i, userContext.reg[i]);
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  }
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  pc = userContext.reg[30];
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  psw = userContext.psw;
282
  mmuSetIndex(userContext.tlbIndex);
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  mmuSetEntryHi(userContext.tlbHi);
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  mmuSetEntryLo(userContext.tlbLo);
285 84 hellwig
  mmuSetBadAddr(userContext.badAddr);
286 59 hellwig
  mmuWriteWord(nextAddr, nextInstr);
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  if (nextAddr == pc) {
288
    return;
289
  }
290
  if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
291
      (mmuGetEntryHi() & 0x80000000) == 0) {
292
    /* TLB user miss */
293
    if (umsrPtr == 0x00000000) {
294
      printf("unexpected TLB user miss exception occurred\n");
295
      return;
296
    }
297
    pc = umsrPtr;
298
  } else {
299
    /* any other exception */
300
    if (isrPtr == 0x00000000) {
301
      printf("unexpected %s occurred\n",
302
             exceptionToString((psw & PSW_PRIO_MASK) >> 16));
303
      return;
304
    }
305
    pc = isrPtr;
306
  }
307
}
308
 
309
 
310
void cpuRun(void) {
311
  Word instr;
312
  int i;
313
  MonitorState runState;
314
  MonitorState *origReturn;
315
 
316
  if (breakSet && breakAddr == pc) {
317
    /* single-step one instruction */
318
    cpuStep();
319
  }
320
  while (1) {
321
    if (breakSet) {
322
      instr = mmuReadWord(breakAddr);
323
      mmuWriteWord(breakAddr, BREAK);
324
    }
325
    for (i = 0; i < 32; i++) {
326
      userContext.reg[i] = RR(i);
327
    }
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    userContext.reg[30] = pc;
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    userContext.psw = psw;
330
    userContext.tlbIndex = mmuGetIndex();
331
    userContext.tlbHi = mmuGetEntryHi();
332
    userContext.tlbLo = mmuGetEntryLo();
333 84 hellwig
    userContext.badAddr = mmuGetBadAddr();
334 59 hellwig
    if (saveState(&runState)) {
335
      origReturn = monitorReturn;
336
      monitorReturn = &runState;
337
      resume();
338
    }
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    monitorReturn = origReturn;
340
    for (i = 0; i < 32; i++) {
341
      WR(i, userContext.reg[i]);
342
    }
343
    pc = userContext.reg[30];
344
    psw = userContext.psw;
345
    mmuSetIndex(userContext.tlbIndex);
346
    mmuSetEntryHi(userContext.tlbHi);
347
    mmuSetEntryLo(userContext.tlbLo);
348 84 hellwig
    mmuSetBadAddr(userContext.badAddr);
349 59 hellwig
    if (breakSet) {
350
      mmuWriteWord(breakAddr, instr);
351
    }
352
    if (breakSet && breakAddr == pc) {
353
      return;
354
    }
355
    if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
356
        (mmuGetEntryHi() & 0x80000000) == 0) {
357
      /* TLB user miss */
358
      if (umsrPtr == 0x00000000) {
359
        printf("unexpected TLB user miss exception occurred\n");
360
        return;
361
      }
362
      pc = umsrPtr;
363
    } else {
364
      /* any other exception */
365
      if (isrPtr == 0x00000000) {
366
        printf("unexpected %s occurred\n",
367
               exceptionToString((psw & PSW_PRIO_MASK) >> 16));
368
        return;
369
      }
370
      pc = isrPtr;
371
    }
372
  }
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}

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