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[/] [eco32/] [trunk/] [monitor/] [monitor/] [common/] [cpu.c] - Blame information for rev 317

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Line No. Rev Author Line
1 59 hellwig
/*
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 * cpu.c -- execute instructions
3
 */
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5
 
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#include "common.h"
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#include "stdarg.h"
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#include "romlib.h"
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#include "instr.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "start.h"
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#define RR(n)           r[n]
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#define WR(n,d)         ((void) ((n) != 0 ? r[n] = (d) : (d)))
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18 200 hellwig
#define BREAK           ((OP_TRAP << 26) | 0x0001)
19 59 hellwig
 
20
 
21
/**************************************************************/
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23
 
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static Word pc;                 /* program counter */
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static Word psw;                /* processor status word */
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static Word r[32];              /* general purpose registers */
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28
static Bool breakSet;           /* breakpoint set if true */
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static Word breakAddr;          /* if breakSet, this is where */
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31
 
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/**************************************************************/
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34
 
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Word cpuGetPC(void) {
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  return pc;
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}
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39
 
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void cpuSetPC(Word addr) {
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  pc = addr;
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}
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44
 
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Word cpuGetReg(int regnum) {
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  return RR(regnum & 0x1F);
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}
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49
 
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void cpuSetReg(int regnum, Word value) {
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  WR(regnum & 0x1F, value);
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}
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54
 
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Word cpuGetPSW(void) {
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  return psw;
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}
58
 
59
 
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void cpuSetPSW(Word value) {
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  psw = value;
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}
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64
 
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Bool cpuTestBreak(void) {
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  return breakSet;
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}
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69
 
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Word cpuGetBreak(void) {
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  return breakAddr;
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}
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74
 
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void cpuSetBreak(Word addr) {
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  breakAddr = addr;
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  breakSet = true;
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}
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80
 
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void cpuResetBreak(void) {
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  breakSet = false;
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}
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85
 
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/**************************************************************/
87
 
88
 
89
static char *cause[32] = {
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  /*  0 */  "serial line 0 xmt interrupt",
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  /*  1 */  "serial line 0 rcv interrupt",
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  /*  2 */  "serial line 1 xmt interrupt",
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  /*  3 */  "serial line 1 rcv interrupt",
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  /*  4 */  "keyboard interrupt",
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  /*  5 */  "unknown interrupt",
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  /*  6 */  "unknown interrupt",
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  /*  7 */  "unknown interrupt",
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  /*  8 */  "disk interrupt",
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  /*  9 */  "unknown interrupt",
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  /* 10 */  "unknown interrupt",
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  /* 11 */  "unknown interrupt",
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  /* 12 */  "unknown interrupt",
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  /* 13 */  "unknown interrupt",
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  /* 14 */  "timer 0 interrupt",
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  /* 15 */  "timer 1 interrupt",
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  /* 16 */  "bus timeout exception",
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  /* 17 */  "illegal instruction exception",
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  /* 18 */  "privileged instruction exception",
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  /* 19 */  "divide instruction exception",
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  /* 20 */  "trap instruction exception",
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  /* 21 */  "TLB miss exception",
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  /* 22 */  "TLB write exception",
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  /* 23 */  "TLB invalid exception",
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  /* 24 */  "illegal address exception",
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  /* 25 */  "privileged address exception",
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  /* 26 */  "unknown exception",
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  /* 27 */  "unknown exception",
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  /* 28 */  "unknown exception",
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  /* 29 */  "unknown exception",
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  /* 30 */  "unknown exception",
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  /* 31 */  "unknown exception"
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};
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char *exceptionToString(int exception) {
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  if (exception < 0 ||
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      exception >= sizeof(cause)/sizeof(cause[0])) {
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    return "<exception number out of bounds>";
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  }
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  return cause[exception];
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}
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134
/**************************************************************/
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136
 
137
static Byte stepType[64] = {
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  /*          0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  */
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  /* 0x00 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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  /* 0x10 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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  /* 0x20 */  2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 4, 3, 4, 1, 0,
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  /* 0x30 */  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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};
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145
 
146
static Bool evalCond(int cc, Word a, Word b) {
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  switch (cc) {
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    case 0:
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      /* equal */
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      if (a == b) {
151
        return true;
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      }
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      break;
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    case 1:
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      /* not equal */
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      if (a != b) {
157
        return true;
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      }
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      break;
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    case 2:
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      /* less or equal (signed) */
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      if ((signed int) a <= (signed int) b) {
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        return true;
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      }
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      break;
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    case 3:
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      /* less or equal (unsigned) */
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      if (a <= b) {
169
        return true;
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      }
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      break;
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    case 4:
173
      /* less than (signed) */
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      if ((signed int) a < (signed int) b) {
175
        return true;
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      }
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      break;
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    case 5:
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      /* less than (unsigned) */
180
      if (a < b) {
181
        return true;
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      }
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      break;
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    case 6:
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      /* greater or equal (signed) */
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      if ((signed int) a >= (signed int) b) {
187
        return true;
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      }
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      break;
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    case 7:
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      /* greater or equal (unsigned) */
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      if (a >= b) {
193
        return true;
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      }
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      break;
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    case 8:
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      /* greater than (signed) */
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      if ((signed int) a > (signed int) b) {
199
        return true;
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      }
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      break;
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    case 9:
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      /* greater than (unsigned) */
204
      if (a > b) {
205
        return true;
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      }
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      break;
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    default:
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      /* this should never happen */
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      printf("cannot compute condition code %d\n", cc);
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      break;
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  }
213
  return false;
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}
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216
 
217
void cpuStep(void) {
218
  Word instr;
219
  int opcode;
220
  int reg1, reg2;
221
  Half immed;
222
  Word offset;
223
  Word nextAddr;
224
  Word nextInstr;
225
  int i;
226
  MonitorState stepState;
227
  MonitorState *origReturn;
228
 
229
  instr = mmuReadWord(pc);
230
  opcode = (instr >> 26) & 0x3F;
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  reg1 = (instr >> 21) & 0x1F;
232
  reg2 = (instr >> 16) & 0x1F;
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  immed = instr & 0x0000FFFF;
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  offset = instr & 0x03FFFFFF;
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  switch (stepType[opcode]) {
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    case 1:
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      /* next instruction follows current one immediately */
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      nextAddr = pc + 4;
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      break;
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    case 2:
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      /* next instruction conditionally reached by PC relative branch */
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      nextAddr = pc + 4;
243
      if (evalCond(opcode - OP_BEQ, RR(reg1), RR(reg2))) {
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        nextAddr += SEXT16(immed) << 2;
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      }
246
      break;
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    case 3:
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      /* next instruction reached by PC relative jump */
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      nextAddr = pc + 4 + (SEXT26(offset) << 2);
250
      break;
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    case 4:
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      /* next instruction reached by jump to register contents */
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      nextAddr = RR(reg1) & 0xFFFFFFFC;
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      break;
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    default:
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      printf("cannot single-step instruction with opcode 0x%02X\n",
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             opcode);
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      return;
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  }
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  nextInstr = mmuReadWord(nextAddr);
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  mmuWriteWord(nextAddr, BREAK);
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  for (i = 0; i < 32; i++) {
263
    userContext.reg[i] = RR(i);
264
  }
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  userContext.reg[30] = pc;
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  userContext.psw = psw;
267
  userContext.tlbIndex = mmuGetIndex();
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  userContext.tlbHi = mmuGetEntryHi();
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  userContext.tlbLo = mmuGetEntryLo();
270 84 hellwig
  userContext.badAddr = mmuGetBadAddr();
271 180 hellwig
  userContext.badAccs = mmuGetBadAccs();
272 59 hellwig
  if (saveState(&stepState)) {
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    origReturn = monitorReturn;
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    monitorReturn = &stepState;
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    resume();
276
  }
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  monitorReturn = origReturn;
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  for (i = 0; i < 32; i++) {
279
    WR(i, userContext.reg[i]);
280
  }
281
  pc = userContext.reg[30];
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  psw = userContext.psw;
283
  mmuSetIndex(userContext.tlbIndex);
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  mmuSetEntryHi(userContext.tlbHi);
285
  mmuSetEntryLo(userContext.tlbLo);
286 84 hellwig
  mmuSetBadAddr(userContext.badAddr);
287 180 hellwig
  mmuSetBadAccs(userContext.badAccs);
288 59 hellwig
  mmuWriteWord(nextAddr, nextInstr);
289
  if (nextAddr == pc) {
290
    return;
291
  }
292
  if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
293
      (mmuGetEntryHi() & 0x80000000) == 0) {
294
    /* TLB user miss */
295 182 hellwig
    printf("unexpected TLB user miss exception occurred\n");
296
    return;
297 59 hellwig
  } else {
298
    /* any other exception */
299 182 hellwig
    printf("unexpected %s occurred\n",
300
           exceptionToString((psw & PSW_PRIO_MASK) >> 16));
301
    return;
302 59 hellwig
  }
303
}
304
 
305
 
306
void cpuRun(void) {
307
  Word instr;
308
  int i;
309
  MonitorState runState;
310
  MonitorState *origReturn;
311
 
312
  if (breakSet && breakAddr == pc) {
313
    /* single-step one instruction */
314
    cpuStep();
315
  }
316
  while (1) {
317
    if (breakSet) {
318
      instr = mmuReadWord(breakAddr);
319
      mmuWriteWord(breakAddr, BREAK);
320
    }
321
    for (i = 0; i < 32; i++) {
322
      userContext.reg[i] = RR(i);
323
    }
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    userContext.reg[30] = pc;
325
    userContext.psw = psw;
326
    userContext.tlbIndex = mmuGetIndex();
327
    userContext.tlbHi = mmuGetEntryHi();
328
    userContext.tlbLo = mmuGetEntryLo();
329 84 hellwig
    userContext.badAddr = mmuGetBadAddr();
330 180 hellwig
    userContext.badAccs = mmuGetBadAccs();
331 59 hellwig
    if (saveState(&runState)) {
332
      origReturn = monitorReturn;
333
      monitorReturn = &runState;
334
      resume();
335
    }
336
    monitorReturn = origReturn;
337
    for (i = 0; i < 32; i++) {
338
      WR(i, userContext.reg[i]);
339
    }
340
    pc = userContext.reg[30];
341
    psw = userContext.psw;
342
    mmuSetIndex(userContext.tlbIndex);
343
    mmuSetEntryHi(userContext.tlbHi);
344
    mmuSetEntryLo(userContext.tlbLo);
345 84 hellwig
    mmuSetBadAddr(userContext.badAddr);
346 180 hellwig
    mmuSetBadAccs(userContext.badAccs);
347 59 hellwig
    if (breakSet) {
348
      mmuWriteWord(breakAddr, instr);
349
    }
350
    if (breakSet && breakAddr == pc) {
351
      return;
352
    }
353
    if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
354
        (mmuGetEntryHi() & 0x80000000) == 0) {
355
      /* TLB user miss */
356 182 hellwig
      printf("unexpected TLB user miss exception occurred\n");
357
      return;
358 59 hellwig
    } else {
359
      /* any other exception */
360 182 hellwig
      printf("unexpected %s occurred\n",
361
             exceptionToString((psw & PSW_PRIO_MASK) >> 16));
362
      return;
363 59 hellwig
    }
364
  }
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}

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