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[/] [eco32/] [trunk/] [monitor/] [monitor/] [common/] [mmu.c] - Blame information for rev 128

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Line No. Rev Author Line
1 59 hellwig
/*
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 * mmu.c -- memory and TLB access
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 */
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#include "common.h"
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#include "stdarg.h"
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#include "romlib.h"
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#include "mmu.h"
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#include "start.h"
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static Word tlbIndex;
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static Word tlbEntryHi;
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static Word tlbEntryLo;
16 84 hellwig
static Word badAddress;
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Word mmuReadWord(Word vAddr) {
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  return *(Word *)vAddr;
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}
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Half mmuReadHalf(Word vAddr) {
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  return *(Half *)vAddr;
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}
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Byte mmuReadByte(Word vAddr) {
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  return *(Byte *)vAddr;
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}
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void mmuWriteWord(Word vAddr, Word data) {
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  *(Word *)vAddr = data;
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}
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void mmuWriteHalf(Word vAddr, Half data) {
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  *(Half *)vAddr = data;
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}
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void mmuWriteByte(Word vAddr, Byte data) {
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  *(Byte *)vAddr = data;
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}
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Word mmuGetIndex(void) {
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  return tlbIndex;
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}
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void mmuSetIndex(Word value) {
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  tlbIndex = value;
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}
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Word mmuGetEntryHi(void) {
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  return tlbEntryHi;
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}
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void mmuSetEntryHi(Word value) {
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  tlbEntryHi = value;
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}
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Word mmuGetEntryLo(void) {
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  return tlbEntryLo;
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}
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void mmuSetEntryLo(Word value) {
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  tlbEntryLo = value;
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}
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Word mmuGetBadAddr(void) {
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  return badAddress;
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}
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void mmuSetBadAddr(Word value) {
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  badAddress = value;
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}
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TLB_Entry mmuGetTLB(int index) {
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  Word hi;
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  Word lo;
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  TLB_Entry result;
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  hi = getTLB_HI(index);
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  lo = getTLB_LO(index);
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  result.page = hi & PAGE_MASK;
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  result.frame = lo & PAGE_MASK;
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  result.write = (lo & TLB_WRITE) ? true : false;
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  result.valid = (lo & TLB_VALID) ? true : false;
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  return result;
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}
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void mmuSetTLB(int index, TLB_Entry tlbEntry) {
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  Word flags;
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  flags = 0;
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  if (tlbEntry.write) {
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    flags |= TLB_WRITE;
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  }
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  if (tlbEntry.valid) {
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    flags |= TLB_VALID;
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  }
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  setTLB(index, tlbEntry.page, tlbEntry.frame | flags);
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}

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