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[/] [eco32/] [trunk/] [sim/] [mmu.h] - Blame information for rev 157

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Line No. Rev Author Line
1 8 hellwig
/*
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 * mmu.h -- MMU simulation
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 */
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#ifndef _MMU_H_
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#define _MMU_H_
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#define TLB_SHFT        5               /* log2 of number of TLB entries */
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#define TLB_SIZE        (1 << TLB_SHFT) /* total number of TLB entries */
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#define TLB_MASK        (TLB_SIZE - 1)  /* mask for number of TLB entries */
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#define TLB_FIXED       4               /* number of fixed TLB entries */
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#define TLB_WRITE       (1 << 1)        /* write bit in EntryLo */
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#define TLB_VALID       (1 << 0)        /* valid bit in EntryLo */
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typedef struct {
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  Word page;            /* 20 high-order bits of virtual address */
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  Word frame;           /* 20 high-order bits of physical address */
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  Bool write;           /* must be true to allow writing to the page */
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  Bool valid;           /* must be true for the entry to be valid */
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} TLB_Entry;
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Word mmuReadWord(Word vAddr, Bool userMode);
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Half mmuReadHalf(Word vAddr, Bool userMode);
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Byte mmuReadByte(Word vAddr, Bool userMode);
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void mmuWriteWord(Word vAddr, Word data, Bool userMode);
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void mmuWriteHalf(Word vAddr, Half data, Bool userMode);
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void mmuWriteByte(Word vAddr, Byte data, Bool userMode);
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Word mmuGetIndex(void);
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void mmuSetIndex(Word value);
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Word mmuGetEntryHi(void);
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void mmuSetEntryHi(Word value);
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Word mmuGetEntryLo(void);
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void mmuSetEntryLo(Word value);
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Word mmuGetBadAddr(void);
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void mmuSetBadAddr(Word value);
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void mmuTbs(void);
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void mmuTbwr(void);
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void mmuTbri(void);
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void mmuTbwi(void);
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TLB_Entry mmuGetTLB(int index);
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void mmuSetTLB(int index, TLB_Entry tlbEntry);
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void mmuReset(void);
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void mmuInit(void);
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void mmuExit(void);
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#endif /* _MMU_H_ */

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