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Subversion Repositories eco32

[/] [eco32/] [trunk/] [stdalone/] [memsize/] [start.s] - Blame information for rev 100

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;
; start.s -- startup code
;
 
        .import main
        .import _ecode
        .import _edata
        .import _ebss
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export enable
        .export disable
        .export getISR
        .export setISR
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
        .code
 
        ; reset arrives here
reset:
        j       start
 
        ; interrupts arrive here
intrpt:
        j       isr
 
        ; user TLB misses arrive here
userMiss:
        j       userMiss
 
isr:
        add     $26,$29,$0       ; sp -> $26
        add     $27,$1,$0        ; $1 -> $27
        add     $29,$0,istack    ; set stack
        sub     $29,$29,108
        stw     $2,$29,0 ; save registers
        stw     $3,$29,4
        stw     $4,$29,8
        stw     $5,$29,12
        stw     $6,$29,16
        stw     $7,$29,20
        stw     $8,$29,24
        stw     $9,$29,28
        stw     $10,$29,32
        stw     $11,$29,36
        stw     $12,$29,40
        stw     $13,$29,44
        stw     $14,$29,48
        stw     $15,$29,52
        stw     $16,$29,56
        stw     $17,$29,60
        stw     $18,$29,64
        stw     $19,$29,68
        stw     $20,$29,72
        stw     $21,$29,76
        stw     $22,$29,80
        stw     $23,$29,84
        stw     $24,$29,88
        stw     $25,$29,92
        stw     $26,$29,96
        stw     $27,$29,100
        stw     $31,$29,104
        mvfs    $4,0             ; $4 = IRQ number
        slr     $4,$4,16
        and     $4,$4,0x1F
        sll     $26,$4,2        ; $26 = 4 * IRQ number
        ldw     $26,$26,irqsrv  ; get addr of service routine
        jalr    $26             ; call service routine
        beq     $2,$0,resume     ; resume instruction if ISR returned 0
        add     $30,$30,4       ; else skip offending instruction
resume:
        ldw     $2,$29,0
        ldw     $3,$29,4
        ldw     $4,$29,8
        ldw     $5,$29,12
        ldw     $6,$29,16
        ldw     $7,$29,20
        ldw     $8,$29,24
        ldw     $9,$29,28
        ldw     $10,$29,32
        ldw     $11,$29,36
        ldw     $12,$29,40
        ldw     $13,$29,44
        ldw     $14,$29,48
        ldw     $15,$29,52
        ldw     $16,$29,56
        ldw     $17,$29,60
        ldw     $18,$29,64
        ldw     $19,$29,68
        ldw     $20,$29,72
        ldw     $21,$29,76
        ldw     $22,$29,80
        ldw     $23,$29,84
        ldw     $24,$29,88
        ldw     $25,$29,92
        ldw     $26,$29,96
        ldw     $27,$29,100
        ldw     $31,$29,104
        add     $1,$27,$0        ; $27 -> $1
        add     $29,$26,0        ; $26 -> sp
        rfx                     ; return from exception
 
start:
        add     $8,$0,0xA8003FFF
        add     $9,$0,0xC0000000
        stw     $8,$9,0          ; 0xC0000000: j 0xC0010000
        stw     $8,$9,4         ; 0xC0000004: j 0xC0010004
        stw     $8,$9,8         ; 0xC0000008: j 0xC0010008
        mvfs    $8,0
        or      $8,$8,1 << 27   ; let vector point to RAM
        mvts    $8,0
        add     $29,$0,stack     ; set sp
        add     $10,$0,_bdata    ; copy data segment
        add     $8,$0,_edata
        sub     $9,$8,$10
        add     $9,$9,_ecode
        j       cpytest
cpyloop:
        ldw     $11,$9,0
        stw     $11,$8,0
cpytest:
        sub     $8,$8,4
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
        add     $8,$0,_bbss      ; clear bss
        add     $9,$0,_ebss
        j       clrtest
clrloop:
        stw     $0,$8,0
        add     $8,$8,4
clrtest:
        bltu    $8,$9,clrloop
        jal     main            ; call 'main'
start1:
        j       start1          ; loop
 
enable:
        mvfs    $8,0
        or      $8,$8,1 << 23
        mvts    $8,0
        jr      $31
 
disable:
        mvfs    $8,0
        and     $8,$8,~(1 << 23)
        mvts    $8,0
        jr      $31
 
getISR:
        sll     $4,$4,2
        ldw     $2,$4,irqsrv
        jr      $31
 
setISR:
        sll     $4,$4,2
        stw     $5,$4,irqsrv
        jr      $31
 
        .data
 
; interrupt service routine table
 
        .align  4
 
irqsrv:
        .word   0                ; 00: terminal 0 transmitter interrupt
        .word   0                ; 01: terminal 0 receiver interrupt
        .word   0                ; 02: terminal 1 transmitter interrupt
        .word   0                ; 03: terminal 1 receiver interrupt
        .word   0                ; 04: keyboard interrupt
        .word   0                ; 05: unused
        .word   0                ; 06: unused
        .word   0                ; 07: unused
        .word   0                ; 08: disk interrupt
        .word   0                ; 09: unused
        .word   0                ; 10: unused
        .word   0                ; 11: unused
        .word   0                ; 12: unused
        .word   0                ; 13: unused
        .word   0                ; 14: timer 0 interrupt
        .word   0                ; 15: timer 1 interrupt
        .word   0                ; 16: bus timeout exception
        .word   0                ; 17: illegal instruction exception
        .word   0                ; 18: privileged instruction exception
        .word   0                ; 19: divide instruction exception
        .word   0                ; 20: trap instruction exception
        .word   0                ; 21: TLB miss exception
        .word   0                ; 22: TLB write exception
        .word   0                ; 23: TLB invalid exception
        .word   0                ; 24: illegal address exception
        .word   0                ; 25: privileged address exception
        .word   0                ; 26: unused
        .word   0                ; 27: unused
        .word   0                ; 28: unused
        .word   0                ; 29: unused
        .word   0                ; 30: unused
        .word   0                ; 31: unused
 
        .bss
 
        .align  4
        .space  0x800
stack:
 
        .align  4
        .space  0x800
istack:

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [stdalone/] [memsize/] [start.s] - Blame information for rev 100

Line No.	Rev	Author	Line
1	18	hellwig	`;`
2			`; start.s -- startup code`
3			`;`
4
5			`.import main`
6			`.import _ecode`
7			`.import _edata`
8			`.import _ebss`
9
10			`.export _bcode`
11			`.export _bdata`
12			`.export _bbss`
13
14			`.export enable`
15			`.export disable`
16			`.export getISR`
17			`.export setISR`
18
19			`.code`
20			`_bcode:`
21
22			`.data`
23			`_bdata:`
24
25			`.bss`
26			`_bbss:`
27
28			`.code`
29
30			`; reset arrives here`
31			`reset:`
32			`j start`
33
34			`; interrupts arrive here`
35			`intrpt:`
36			`j isr`
37
38			`; user TLB misses arrive here`
39			`userMiss:`
40			`j userMiss`
41
42			`isr:`
43			`add $26,$29,$0 ; sp -> $26`
44			`add $27,$1,$0 ; $1 -> $27`
45			`add $29,$0,istack ; set stack`
46			`sub $29,$29,108`
47			`stw $2,$29,0 ; save registers`
48			`stw $3,$29,4`
49			`stw $4,$29,8`
50			`stw $5,$29,12`
51			`stw $6,$29,16`
52			`stw $7,$29,20`
53			`stw $8,$29,24`
54			`stw $9,$29,28`
55			`stw $10,$29,32`
56			`stw $11,$29,36`
57			`stw $12,$29,40`
58			`stw $13,$29,44`
59			`stw $14,$29,48`
60			`stw $15,$29,52`
61			`stw $16,$29,56`
62			`stw $17,$29,60`
63			`stw $18,$29,64`
64			`stw $19,$29,68`
65			`stw $20,$29,72`
66			`stw $21,$29,76`
67			`stw $22,$29,80`
68			`stw $23,$29,84`
69			`stw $24,$29,88`
70			`stw $25,$29,92`
71			`stw $26,$29,96`
72			`stw $27,$29,100`
73			`stw $31,$29,104`
74			`mvfs $4,0 ; $4 = IRQ number`
75			`slr $4,$4,16`
76			`and $4,$4,0x1F`
77			`sll $26,$4,2 ; $26 = 4 * IRQ number`
78			`ldw $26,$26,irqsrv ; get addr of service routine`
79			`jalr $26 ; call service routine`
80			`beq $2,$0,resume ; resume instruction if ISR returned 0`
81			`add $30,$30,4 ; else skip offending instruction`
82			`resume:`
83			`ldw $2,$29,0`
84			`ldw $3,$29,4`
85			`ldw $4,$29,8`
86			`ldw $5,$29,12`
87			`ldw $6,$29,16`
88			`ldw $7,$29,20`
89			`ldw $8,$29,24`
90			`ldw $9,$29,28`
91			`ldw $10,$29,32`
92			`ldw $11,$29,36`
93			`ldw $12,$29,40`
94			`ldw $13,$29,44`
95			`ldw $14,$29,48`
96			`ldw $15,$29,52`
97			`ldw $16,$29,56`
98			`ldw $17,$29,60`
99			`ldw $18,$29,64`
100			`ldw $19,$29,68`
101			`ldw $20,$29,72`
102			`ldw $21,$29,76`
103			`ldw $22,$29,80`
104			`ldw $23,$29,84`
105			`ldw $24,$29,88`
106			`ldw $25,$29,92`
107			`ldw $26,$29,96`
108			`ldw $27,$29,100`
109			`ldw $31,$29,104`
110			`add $1,$27,$0 ; $27 -> $1`
111			`add $29,$26,0 ; $26 -> sp`
112			`rfx ; return from exception`
113
114			`start:`
115	96	hellwig	`add $8,$0,0xA8003FFF`
116			`add $9,$0,0xC0000000`
117			`stw $8,$9,0 ; 0xC0000000: j 0xC0010000`
118			`stw $8,$9,4 ; 0xC0000004: j 0xC0010004`
119			`stw $8,$9,8 ; 0xC0000008: j 0xC0010008`
120	18	hellwig	`mvfs $8,0`
121			`or $8,$8,1 << 27 ; let vector point to RAM`
122			`mvts $8,0`
123			`add $29,$0,stack ; set sp`
124			`add $10,$0,_bdata ; copy data segment`
125			`add $8,$0,_edata`
126			`sub $9,$8,$10`
127			`add $9,$9,_ecode`
128			`j cpytest`
129			`cpyloop:`
130			`ldw $11,$9,0`
131			`stw $11,$8,0`
132			`cpytest:`
133			`sub $8,$8,4`
134			`sub $9,$9,4`
135			`bgeu $8,$10,cpyloop`
136			`add $8,$0,_bbss ; clear bss`
137			`add $9,$0,_ebss`
138			`j clrtest`
139			`clrloop:`
140			`stw $0,$8,0`
141			`add $8,$8,4`
142			`clrtest:`
143			`bltu $8,$9,clrloop`
144			`jal main ; call 'main'`
145			`start1:`
146			`j start1 ; loop`
147
148			`enable:`
149			`mvfs $8,0`
150			`or $8,$8,1 << 23`
151			`mvts $8,0`
152			`jr $31`
153
154			`disable:`
155			`mvfs $8,0`
156			`and $8,$8,~(1 << 23)`
157			`mvts $8,0`
158			`jr $31`
159
160			`getISR:`
161			`sll $4,$4,2`
162			`ldw $2,$4,irqsrv`
163			`jr $31`
164
165			`setISR:`
166			`sll $4,$4,2`
167			`stw $5,$4,irqsrv`
168			`jr $31`
169
170			`.data`
171
172			`; interrupt service routine table`
173
174			`.align 4`
175
176			`irqsrv:`
177			`.word 0 ; 00: terminal 0 transmitter interrupt`
178			`.word 0 ; 01: terminal 0 receiver interrupt`
179			`.word 0 ; 02: terminal 1 transmitter interrupt`
180			`.word 0 ; 03: terminal 1 receiver interrupt`
181			`.word 0 ; 04: keyboard interrupt`
182			`.word 0 ; 05: unused`
183			`.word 0 ; 06: unused`
184			`.word 0 ; 07: unused`
185			`.word 0 ; 08: disk interrupt`
186			`.word 0 ; 09: unused`
187			`.word 0 ; 10: unused`
188			`.word 0 ; 11: unused`
189			`.word 0 ; 12: unused`
190			`.word 0 ; 13: unused`
191	38	hellwig	`.word 0 ; 14: timer 0 interrupt`
192			`.word 0 ; 15: timer 1 interrupt`
193	18	hellwig	`.word 0 ; 16: bus timeout exception`
194			`.word 0 ; 17: illegal instruction exception`
195			`.word 0 ; 18: privileged instruction exception`
196			`.word 0 ; 19: divide instruction exception`
197			`.word 0 ; 20: trap instruction exception`
198			`.word 0 ; 21: TLB miss exception`
199			`.word 0 ; 22: TLB write exception`
200			`.word 0 ; 23: TLB invalid exception`
201			`.word 0 ; 24: illegal address exception`
202			`.word 0 ; 25: privileged address exception`
203			`.word 0 ; 26: unused`
204			`.word 0 ; 27: unused`
205			`.word 0 ; 28: unused`
206			`.word 0 ; 29: unused`
207			`.word 0 ; 30: unused`
208			`.word 0 ; 31: unused`
209
210			`.bss`
211
212			`.align 4`
213			`.space 0x800`
214			`stack:`
215
216			`.align 4`
217			`.space 0x800`
218			`istack:`