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Subversion Repositories eco32

[/] [eco32/] [trunk/] [stdalone/] [onetask/] [os/] [start.s] - Blame information for rev 18

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;
; start.s -- startup code
;
 
        .import main
        .import _ecode
        .import _edata
        .import _ebss
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export enable
        .export disable
        .export getISR
        .export setISR
        .export startTask
        .export setTLB
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
        .code
 
        ; reset arrives here
reset:
        j       start
 
        ; interrupts arrive here
intrpt:
        j       isr
 
        ; user TLB misses arrive here
userMiss:
        j       userMiss
 
isr:
        add     $26,$29,$0       ; sp -> $26
        add     $27,$1,$0        ; $1 -> $27
        add     $29,$0,istack    ; setup interrupt stack
        sub     $29,$29,128     ; save registers
        stw     $2,$29,8
        stw     $3,$29,12
        stw     $4,$29,16
        stw     $5,$29,20
        stw     $6,$29,24
        stw     $7,$29,28
        stw     $8,$29,32
        stw     $9,$29,36
        stw     $10,$29,40
        stw     $11,$29,44
        stw     $12,$29,48
        stw     $13,$29,52
        stw     $14,$29,56
        stw     $15,$29,60
        stw     $16,$29,64
        stw     $17,$29,68
        stw     $18,$29,72
        stw     $19,$29,76
        stw     $20,$29,80
        stw     $21,$29,84
        stw     $22,$29,88
        stw     $23,$29,92
        stw     $24,$29,96
        stw     $25,$29,100
        stw     $26,$29,116     ; this is the task's sp
        stw     $27,$29,4       ; this is the task's $1
        stw     $30,$29,120     ; this is the task's resumption address
        stw     $31,$29,124
        add     $5,$29,$0        ; $5 = pointer to register array
        mvfs    $4,0             ; $4 = IRQ number
        slr     $4,$4,16
        and     $4,$4,0x1F
        sll     $26,$4,2        ; $26 = 4 * IRQ number
        ldw     $26,$26,irqsrv  ; get addr of service routine
        jalr    $26             ; call service routine
        j       resume          ; resume interrupted task if ISR returns
 
        ; resume a task
resume:
        ldw     $2,$29,8        ; restore registers
        ldw     $3,$29,12
        ldw     $4,$29,16
        ldw     $5,$29,20
        ldw     $6,$29,24
        ldw     $7,$29,28
        ldw     $8,$29,32
        ldw     $9,$29,36
        ldw     $10,$29,40
        ldw     $11,$29,44
        ldw     $12,$29,48
        ldw     $13,$29,52
        ldw     $14,$29,56
        ldw     $15,$29,60
        ldw     $16,$29,64
        ldw     $17,$29,68
        ldw     $18,$29,72
        ldw     $19,$29,76
        ldw     $20,$29,80
        ldw     $21,$29,84
        ldw     $22,$29,88
        ldw     $23,$29,92
        ldw     $24,$29,96
        ldw     $25,$29,100
        ldw     $26,$29,116     ; this is the task's sp
        ldw     $27,$29,4       ; this is the task's $1
        ldw     $30,$29,120     ; this is the task's resumption address
        ldw     $31,$29,124
        add     $1,$27,$0        ; $27 -> $1
        add     $29,$26,$0       ; $26 -> sp
        rfx                     ; return from exception
 
start:
        mvfs    $8,0
        or      $8,$8,1 << 27   ; let vector point to RAM
        mvts    $8,0
        add     $29,$0,stack     ; set sp
        add     $10,$0,_bdata    ; copy data segment
        add     $8,$0,_edata
        sub     $9,$8,$10
        add     $9,$9,_ecode
        j       cpytest
cpyloop:
        ldw     $11,$9,0
        stw     $11,$8,0
cpytest:
        sub     $8,$8,4
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
        add     $8,$0,_bbss      ; clear bss
        add     $9,$0,_ebss
        j       clrtest
clrloop:
        stw     $0,$8,0
        add     $8,$8,4
clrtest:
        bltu    $8,$9,clrloop
        jal     main            ; call 'main'
start1:
        j       start1          ; loop
 
enable:
        mvfs    $8,0
        or      $8,$8,1 << 23
        mvts    $8,0
        jr      $31
 
disable:
        mvfs    $8,0
        and     $8,$8,~(1 << 23)
        mvts    $8,0
        jr      $31
 
getISR:
        sll     $4,$4,2
        ldw     $2,$4,irqsrv
        jr      $31
 
setISR:
        sll     $4,$4,2
        stw     $5,$4,irqsrv
        jr      $31
 
startTask:
        or      $29,$4,0xC0000000
        sub     $29,$29,128
        stw     $0,$29,0  ; preset registers
        stw     $0,$29,4
        stw     $0,$29,8
        stw     $0,$29,12
        stw     $0,$29,16
        stw     $0,$29,20
        stw     $0,$29,24
        stw     $0,$29,28
        stw     $0,$29,32
        stw     $0,$29,36
        stw     $0,$29,40
        stw     $0,$29,44
        stw     $0,$29,48
        stw     $0,$29,52
        stw     $0,$29,56
        stw     $0,$29,60
        stw     $0,$29,64
        stw     $0,$29,68
        stw     $0,$29,72
        stw     $0,$29,76
        stw     $0,$29,80
        stw     $0,$29,84
        stw     $0,$29,88
        stw     $0,$29,92
        stw     $0,$29,96
        stw     $0,$29,100
        stw     $0,$29,104
        stw     $0,$29,108
        stw     $0,$29,112
        add     $8,$0,0x80000000
        stw     $8,$29,116      ; sp
        stw     $0,$29,120       ; task starts at virtual address 0
        stw     $0,$29,124
        mvfs    $8,0
        or      $8,$8,1 << 25   ; set previous mode to 'user'
        mvts    $8,0
        j       resume
 
setTLB:
        mvts    $4,1            ; set index
        mvts    $5,2            ; set entryHi
        mvts    $6,3            ; set entryLo
        tbwi                    ; write TLB entry at index
        jr      $31
 
        .data
 
; interrupt service routine table
 
        .align  4
 
irqsrv:
        .word   0                ; 00: terminal 0 transmitter interrupt
        .word   0                ; 01: terminal 0 receiver interrupt
        .word   0                ; 02: terminal 1 transmitter interrupt
        .word   0                ; 03: terminal 1 receiver interrupt
        .word   0                ; 04: keyboard interrupt
        .word   0                ; 05: unused
        .word   0                ; 06: unused
        .word   0                ; 07: unused
        .word   0                ; 08: disk interrupt
        .word   0                ; 09: unused
        .word   0                ; 10: unused
        .word   0                ; 11: unused
        .word   0                ; 12: unused
        .word   0                ; 13: unused
        .word   0                ; 14: timer interrupt
        .word   0                ; 15: unused
        .word   0                ; 16: bus timeout exception
        .word   0                ; 17: illegal instruction exception
        .word   0                ; 18: privileged instruction exception
        .word   0                ; 19: divide instruction exception
        .word   0                ; 20: trap instruction exception
        .word   0                ; 21: TLB miss exception
        .word   0                ; 22: TLB write exception
        .word   0                ; 23: TLB invalid exception
        .word   0                ; 24: illegal address exception
        .word   0                ; 25: privileged address exception
        .word   0                ; 26: unused
        .word   0                ; 27: unused
        .word   0                ; 28: unused
        .word   0                ; 29: unused
        .word   0                ; 30: unused
        .word   0                ; 31: unused
 
        .bss
 
        .align  4
        .space  0x800
stack:
 
        .align  4
        .space  0x800
istack:

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [stdalone/] [onetask/] [os/] [start.s] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	hellwig	`;`
2			`; start.s -- startup code`
3			`;`
4
5			`.import main`
6			`.import _ecode`
7			`.import _edata`
8			`.import _ebss`
9
10			`.export _bcode`
11			`.export _bdata`
12			`.export _bbss`
13
14			`.export enable`
15			`.export disable`
16			`.export getISR`
17			`.export setISR`
18			`.export startTask`
19			`.export setTLB`
20
21			`.code`
22			`_bcode:`
23
24			`.data`
25			`_bdata:`
26
27			`.bss`
28			`_bbss:`
29
30			`.code`
31
32			`; reset arrives here`
33			`reset:`
34			`j start`
35
36			`; interrupts arrive here`
37			`intrpt:`
38			`j isr`
39
40			`; user TLB misses arrive here`
41			`userMiss:`
42			`j userMiss`
43
44			`isr:`
45			`add $26,$29,$0 ; sp -> $26`
46			`add $27,$1,$0 ; $1 -> $27`
47			`add $29,$0,istack ; setup interrupt stack`
48			`sub $29,$29,128 ; save registers`
49			`stw $2,$29,8`
50			`stw $3,$29,12`
51			`stw $4,$29,16`
52			`stw $5,$29,20`
53			`stw $6,$29,24`
54			`stw $7,$29,28`
55			`stw $8,$29,32`
56			`stw $9,$29,36`
57			`stw $10,$29,40`
58			`stw $11,$29,44`
59			`stw $12,$29,48`
60			`stw $13,$29,52`
61			`stw $14,$29,56`
62			`stw $15,$29,60`
63			`stw $16,$29,64`
64			`stw $17,$29,68`
65			`stw $18,$29,72`
66			`stw $19,$29,76`
67			`stw $20,$29,80`
68			`stw $21,$29,84`
69			`stw $22,$29,88`
70			`stw $23,$29,92`
71			`stw $24,$29,96`
72			`stw $25,$29,100`
73			`stw $26,$29,116 ; this is the task's sp`
74			`stw $27,$29,4 ; this is the task's $1`
75			`stw $30,$29,120 ; this is the task's resumption address`
76			`stw $31,$29,124`
77			`add $5,$29,$0 ; $5 = pointer to register array`
78			`mvfs $4,0 ; $4 = IRQ number`
79			`slr $4,$4,16`
80			`and $4,$4,0x1F`
81			`sll $26,$4,2 ; $26 = 4 * IRQ number`
82			`ldw $26,$26,irqsrv ; get addr of service routine`
83			`jalr $26 ; call service routine`
84			`j resume ; resume interrupted task if ISR returns`
85
86			`; resume a task`
87			`resume:`
88			`ldw $2,$29,8 ; restore registers`
89			`ldw $3,$29,12`
90			`ldw $4,$29,16`
91			`ldw $5,$29,20`
92			`ldw $6,$29,24`
93			`ldw $7,$29,28`
94			`ldw $8,$29,32`
95			`ldw $9,$29,36`
96			`ldw $10,$29,40`
97			`ldw $11,$29,44`
98			`ldw $12,$29,48`
99			`ldw $13,$29,52`
100			`ldw $14,$29,56`
101			`ldw $15,$29,60`
102			`ldw $16,$29,64`
103			`ldw $17,$29,68`
104			`ldw $18,$29,72`
105			`ldw $19,$29,76`
106			`ldw $20,$29,80`
107			`ldw $21,$29,84`
108			`ldw $22,$29,88`
109			`ldw $23,$29,92`
110			`ldw $24,$29,96`
111			`ldw $25,$29,100`
112			`ldw $26,$29,116 ; this is the task's sp`
113			`ldw $27,$29,4 ; this is the task's $1`
114			`ldw $30,$29,120 ; this is the task's resumption address`
115			`ldw $31,$29,124`
116			`add $1,$27,$0 ; $27 -> $1`
117			`add $29,$26,$0 ; $26 -> sp`
118			`rfx ; return from exception`
119
120			`start:`
121			`mvfs $8,0`
122			`or $8,$8,1 << 27 ; let vector point to RAM`
123			`mvts $8,0`
124			`add $29,$0,stack ; set sp`
125			`add $10,$0,_bdata ; copy data segment`
126			`add $8,$0,_edata`
127			`sub $9,$8,$10`
128			`add $9,$9,_ecode`
129			`j cpytest`
130			`cpyloop:`
131			`ldw $11,$9,0`
132			`stw $11,$8,0`
133			`cpytest:`
134			`sub $8,$8,4`
135			`sub $9,$9,4`
136			`bgeu $8,$10,cpyloop`
137			`add $8,$0,_bbss ; clear bss`
138			`add $9,$0,_ebss`
139			`j clrtest`
140			`clrloop:`
141			`stw $0,$8,0`
142			`add $8,$8,4`
143			`clrtest:`
144			`bltu $8,$9,clrloop`
145			`jal main ; call 'main'`
146			`start1:`
147			`j start1 ; loop`
148
149			`enable:`
150			`mvfs $8,0`
151			`or $8,$8,1 << 23`
152			`mvts $8,0`
153			`jr $31`
154
155			`disable:`
156			`mvfs $8,0`
157			`and $8,$8,~(1 << 23)`
158			`mvts $8,0`
159			`jr $31`
160
161			`getISR:`
162			`sll $4,$4,2`
163			`ldw $2,$4,irqsrv`
164			`jr $31`
165
166			`setISR:`
167			`sll $4,$4,2`
168			`stw $5,$4,irqsrv`
169			`jr $31`
170
171			`startTask:`
172			`or $29,$4,0xC0000000`
173			`sub $29,$29,128`
174			`stw $0,$29,0 ; preset registers`
175			`stw $0,$29,4`
176			`stw $0,$29,8`
177			`stw $0,$29,12`
178			`stw $0,$29,16`
179			`stw $0,$29,20`
180			`stw $0,$29,24`
181			`stw $0,$29,28`
182			`stw $0,$29,32`
183			`stw $0,$29,36`
184			`stw $0,$29,40`
185			`stw $0,$29,44`
186			`stw $0,$29,48`
187			`stw $0,$29,52`
188			`stw $0,$29,56`
189			`stw $0,$29,60`
190			`stw $0,$29,64`
191			`stw $0,$29,68`
192			`stw $0,$29,72`
193			`stw $0,$29,76`
194			`stw $0,$29,80`
195			`stw $0,$29,84`
196			`stw $0,$29,88`
197			`stw $0,$29,92`
198			`stw $0,$29,96`
199			`stw $0,$29,100`
200			`stw $0,$29,104`
201			`stw $0,$29,108`
202			`stw $0,$29,112`
203			`add $8,$0,0x80000000`
204			`stw $8,$29,116 ; sp`
205			`stw $0,$29,120 ; task starts at virtual address 0`
206			`stw $0,$29,124`
207			`mvfs $8,0`
208			`or $8,$8,1 << 25 ; set previous mode to 'user'`
209			`mvts $8,0`
210			`j resume`
211
212			`setTLB:`
213			`mvts $4,1 ; set index`
214			`mvts $5,2 ; set entryHi`
215			`mvts $6,3 ; set entryLo`
216			`tbwi ; write TLB entry at index`
217			`jr $31`
218
219			`.data`
220
221			`; interrupt service routine table`
222
223			`.align 4`
224
225			`irqsrv:`
226			`.word 0 ; 00: terminal 0 transmitter interrupt`
227			`.word 0 ; 01: terminal 0 receiver interrupt`
228			`.word 0 ; 02: terminal 1 transmitter interrupt`
229			`.word 0 ; 03: terminal 1 receiver interrupt`
230			`.word 0 ; 04: keyboard interrupt`
231			`.word 0 ; 05: unused`
232			`.word 0 ; 06: unused`
233			`.word 0 ; 07: unused`
234			`.word 0 ; 08: disk interrupt`
235			`.word 0 ; 09: unused`
236			`.word 0 ; 10: unused`
237			`.word 0 ; 11: unused`
238			`.word 0 ; 12: unused`
239			`.word 0 ; 13: unused`
240			`.word 0 ; 14: timer interrupt`
241			`.word 0 ; 15: unused`
242			`.word 0 ; 16: bus timeout exception`
243			`.word 0 ; 17: illegal instruction exception`
244			`.word 0 ; 18: privileged instruction exception`
245			`.word 0 ; 19: divide instruction exception`
246			`.word 0 ; 20: trap instruction exception`
247			`.word 0 ; 21: TLB miss exception`
248			`.word 0 ; 22: TLB write exception`
249			`.word 0 ; 23: TLB invalid exception`
250			`.word 0 ; 24: illegal address exception`
251			`.word 0 ; 25: privileged address exception`
252			`.word 0 ; 26: unused`
253			`.word 0 ; 27: unused`
254			`.word 0 ; 28: unused`
255			`.word 0 ; 29: unused`
256			`.word 0 ; 30: unused`
257			`.word 0 ; 31: unused`
258
259			`.bss`
260
261			`.align 4`
262			`.space 0x800`
263			`stack:`
264
265			`.align 4`
266			`.space 0x800`
267			`istack:`