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[/] [eco32/] [trunk/] [stdalone/] [twotasks-2/] [os/] [start.s] - Blame information for rev 124

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;
; start.s -- startup code
;
 
        .import main
        .import task0StkTop
        .import currentStkTop
        .import currentPageDir
        .import _ecode
        .import _edata
        .import _ebss
 
        .export _bcode
        .export _bdata
        .export _bbss
 
        .export enable
        .export disable
        .export orMask
        .export andMask
        .export getISR
        .export setISR
        .export startTask
        .export setTLB
 
        .code
_bcode:
 
        .data
_bdata:
 
        .bss
_bbss:
 
        .code
 
        ; reset arrives here
reset:
        j       start
 
        ; interrupts arrive here
intrpt:
        j       isr
 
        ; user TLB misses arrive here
userMiss:
        add     $27,$1,$0
        ldw     $26,$0,currentPageDir
        mvfs    $1,2
        slr     $1,$1,20
        and     $1,$1,0xFFC
        add     $26,$26,$1
        ldw     $26,$26,0
        mvfs    $1,2
        slr     $1,$1,10
        and     $1,$1,0xFFC
        add     $26,$26,$1
        ldw     $26,$26,0
        mvts    $26,3                   ; entryLow
        tbwr
        add     $1,$27,$0
        rfx
 
isr:
        add     $26,$29,$0               ; sp -> $26
        add     $27,$1,$0                ; $1 -> $27
        ldw     $29,$0,currentStkTop     ; setup kernel mode stack
        sub     $29,$29,128             ; save registers
        stw     $2,$29,8
        stw     $3,$29,12
        stw     $4,$29,16
        stw     $5,$29,20
        stw     $6,$29,24
        stw     $7,$29,28
        stw     $8,$29,32
        stw     $9,$29,36
        stw     $10,$29,40
        stw     $11,$29,44
        stw     $12,$29,48
        stw     $13,$29,52
        stw     $14,$29,56
        stw     $15,$29,60
        stw     $16,$29,64
        stw     $17,$29,68
        stw     $18,$29,72
        stw     $19,$29,76
        stw     $20,$29,80
        stw     $21,$29,84
        stw     $22,$29,88
        stw     $23,$29,92
        stw     $24,$29,96
        stw     $25,$29,100
        stw     $26,$29,116             ; this is the task's sp
        stw     $27,$29,4               ; this is the task's $1
        stw     $30,$29,120             ; this is the task's resumption addr
        stw     $31,$29,124
        add     $5,$29,$0                ; $5 = pointer to register array
        mvfs    $4,0                     ; $4 = IRQ number
        slr     $4,$4,16
        and     $4,$4,0x1F
        sll     $26,$4,2                ; $26 = 4 * IRQ number
        ldw     $26,$26,irqsrv          ; get addr of service routine
        jalr    $26                     ; call service routine
        j       resume                  ; resume task if ISR returns
 
        ; resume a task
resume:
        ldw     $29,$0,currentStkTop     ; setup kernel mode stack
        sub     $29,$29,128             ; restore registers
        ldw     $2,$29,8
        ldw     $3,$29,12
        ldw     $4,$29,16
        ldw     $5,$29,20
        ldw     $6,$29,24
        ldw     $7,$29,28
        ldw     $8,$29,32
        ldw     $9,$29,36
        ldw     $10,$29,40
        ldw     $11,$29,44
        ldw     $12,$29,48
        ldw     $13,$29,52
        ldw     $14,$29,56
        ldw     $15,$29,60
        ldw     $16,$29,64
        ldw     $17,$29,68
        ldw     $18,$29,72
        ldw     $19,$29,76
        ldw     $20,$29,80
        ldw     $21,$29,84
        ldw     $22,$29,88
        ldw     $23,$29,92
        ldw     $24,$29,96
        ldw     $25,$29,100
        ldw     $26,$29,116             ; this is the task's sp
        ldw     $27,$29,4               ; this is the task's $1
        ldw     $30,$29,120             ; this is the task's resumption addr
        ldw     $31,$29,124
        add     $1,$27,$0                ; $27 -> $1
        add     $29,$26,$0               ; $26 -> sp
        rfx                             ; return from exception
 
start:
        add     $8,$0,0xA8003FFF
        add     $9,$0,0xC0000000
        stw     $8,$9,0          ; 0xC0000000: j 0xC0010000
        stw     $8,$9,4         ; 0xC0000004: j 0xC0010004
        stw     $8,$9,8         ; 0xC0000008: j 0xC0010008
        mvfs    $8,0
        or      $8,$8,1 << 27           ; let vector point to RAM
        mvts    $8,0
        add     $10,$0,_bdata            ; copy data segment
        add     $8,$0,_edata
        sub     $9,$8,$10
        add     $9,$9,_ecode
        j       cpytest
cpyloop:
        ldw     $11,$9,0
        stw     $11,$8,0
cpytest:
        sub     $8,$8,4
        sub     $9,$9,4
        bgeu    $8,$10,cpyloop
        add     $8,$0,_bbss              ; clear bss
        add     $9,$0,_ebss
        j       clrtest
clrloop:
        stw     $0,$8,0
        add     $8,$8,4
clrtest:
        bltu    $8,$9,clrloop
        ldw     $29,$0,task0StkTop       ; setup kernel mode stack for task 0
        jal     main                    ; call 'main'
start1:
        j       start1                  ; loop
 
enable:
        mvfs    $8,0
        or      $8,$8,1 << 23
        mvts    $8,0
        jr      $31
 
disable:
        mvfs    $8,0
        and     $8,$8,~(1 << 23)
        mvts    $8,0
        jr      $31
 
orMask:
        mvfs    $8,0
        and     $4,$4,0x0000FFFF        ; use lower 16 bits only
        or      $8,$8,$4
        mvts    $8,0
        jr      $31
 
andMask:
        mvfs    $8,0
        or      $4,$4,0xFFFF0000        ; use lower 16 bits only
        and     $8,$8,$4
        mvts    $8,0
        jr      $31
 
getISR:
        sll     $4,$4,2
        ldw     $2,$4,irqsrv
        jr      $31
 
setISR:
        sll     $4,$4,2
        stw     $5,$4,irqsrv
        jr      $31
 
startTask:
        ldw     $29,$0,currentStkTop     ; setup kernel mode stack
        sub     $29,$29,128
        stw     $0,$29,0          ; preset registers
        stw     $0,$29,4
        stw     $0,$29,8
        stw     $0,$29,12
        stw     $0,$29,16
        stw     $0,$29,20
        stw     $0,$29,24
        stw     $0,$29,28
        stw     $0,$29,32
        stw     $0,$29,36
        stw     $0,$29,40
        stw     $0,$29,44
        stw     $0,$29,48
        stw     $0,$29,52
        stw     $0,$29,56
        stw     $0,$29,60
        stw     $0,$29,64
        stw     $0,$29,68
        stw     $0,$29,72
        stw     $0,$29,76
        stw     $0,$29,80
        stw     $0,$29,84
        stw     $0,$29,88
        stw     $0,$29,92
        stw     $0,$29,96
        stw     $0,$29,100
        stw     $0,$29,104
        stw     $0,$29,108
        stw     $0,$29,112
        add     $8,$0,0x80000000
        stw     $8,$29,116              ; sp
        stw     $0,$29,120               ; task starts at virtual addr 0
        stw     $0,$29,124
        mvfs    $8,0
        or      $8,$8,1 << 25           ; set previous mode to 'user'
        or      $8,$8,1 << 22           ; and enable interrupts
        mvts    $8,0
        j       resume
 
setTLB:
        mvts    $4,1                    ; set index
        mvts    $5,2                    ; set entryHi
        mvts    $6,3                    ; set entryLo
        tbwi                            ; write TLB entry at index
        jr      $31
 
        .data
 
; interrupt service routine table
 
        .align  4
 
irqsrv:
        .word   0                ; 00: terminal 0 transmitter interrupt
        .word   0                ; 01: terminal 0 receiver interrupt
        .word   0                ; 02: terminal 1 transmitter interrupt
        .word   0                ; 03: terminal 1 receiver interrupt
        .word   0                ; 04: keyboard interrupt
        .word   0                ; 05: unused
        .word   0                ; 06: unused
        .word   0                ; 07: unused
        .word   0                ; 08: disk interrupt
        .word   0                ; 09: unused
        .word   0                ; 10: unused
        .word   0                ; 11: unused
        .word   0                ; 12: unused
        .word   0                ; 13: unused
        .word   0                ; 14: timer 0 interrupt
        .word   0                ; 15: timer 1 interrupt
        .word   0                ; 16: bus timeout exception
        .word   0                ; 17: illegal instruction exception
        .word   0                ; 18: privileged instruction exception
        .word   0                ; 19: divide instruction exception
        .word   0                ; 20: trap instruction exception
        .word   0                ; 21: TLB miss exception
        .word   0                ; 22: TLB write exception
        .word   0                ; 23: TLB invalid exception
        .word   0                ; 24: illegal address exception
        .word   0                ; 25: privileged address exception
        .word   0                ; 26: unused
        .word   0                ; 27: unused
        .word   0                ; 28: unused
        .word   0                ; 29: unused
        .word   0                ; 30: unused
        .word   0                ; 31: unused

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Subversion Repositories eco32

[/] [eco32/] [trunk/] [stdalone/] [twotasks-2/] [os/] [start.s] - Blame information for rev 124

Line No.	Rev	Author	Line
1	18	hellwig	`;`
2			`; start.s -- startup code`
3			`;`
4
5			`.import main`
6			`.import task0StkTop`
7			`.import currentStkTop`
8			`.import currentPageDir`
9			`.import _ecode`
10			`.import _edata`
11			`.import _ebss`
12
13			`.export _bcode`
14			`.export _bdata`
15			`.export _bbss`
16
17			`.export enable`
18			`.export disable`
19			`.export orMask`
20			`.export andMask`
21			`.export getISR`
22			`.export setISR`
23			`.export startTask`
24			`.export setTLB`
25
26			`.code`
27			`_bcode:`
28
29			`.data`
30			`_bdata:`
31
32			`.bss`
33			`_bbss:`
34
35			`.code`
36
37			`; reset arrives here`
38			`reset:`
39			`j start`
40
41			`; interrupts arrive here`
42			`intrpt:`
43			`j isr`
44
45			`; user TLB misses arrive here`
46			`userMiss:`
47			`add $27,$1,$0`
48			`ldw $26,$0,currentPageDir`
49			`mvfs $1,2`
50			`slr $1,$1,20`
51			`and $1,$1,0xFFC`
52			`add $26,$26,$1`
53			`ldw $26,$26,0`
54			`mvfs $1,2`
55			`slr $1,$1,10`
56			`and $1,$1,0xFFC`
57			`add $26,$26,$1`
58			`ldw $26,$26,0`
59			`mvts $26,3 ; entryLow`
60			`tbwr`
61			`add $1,$27,$0`
62			`rfx`
63
64			`isr:`
65			`add $26,$29,$0 ; sp -> $26`
66			`add $27,$1,$0 ; $1 -> $27`
67			`ldw $29,$0,currentStkTop ; setup kernel mode stack`
68			`sub $29,$29,128 ; save registers`
69			`stw $2,$29,8`
70			`stw $3,$29,12`
71			`stw $4,$29,16`
72			`stw $5,$29,20`
73			`stw $6,$29,24`
74			`stw $7,$29,28`
75			`stw $8,$29,32`
76			`stw $9,$29,36`
77			`stw $10,$29,40`
78			`stw $11,$29,44`
79			`stw $12,$29,48`
80			`stw $13,$29,52`
81			`stw $14,$29,56`
82			`stw $15,$29,60`
83			`stw $16,$29,64`
84			`stw $17,$29,68`
85			`stw $18,$29,72`
86			`stw $19,$29,76`
87			`stw $20,$29,80`
88			`stw $21,$29,84`
89			`stw $22,$29,88`
90			`stw $23,$29,92`
91			`stw $24,$29,96`
92			`stw $25,$29,100`
93			`stw $26,$29,116 ; this is the task's sp`
94			`stw $27,$29,4 ; this is the task's $1`
95			`stw $30,$29,120 ; this is the task's resumption addr`
96			`stw $31,$29,124`
97			`add $5,$29,$0 ; $5 = pointer to register array`
98			`mvfs $4,0 ; $4 = IRQ number`
99			`slr $4,$4,16`
100			`and $4,$4,0x1F`
101			`sll $26,$4,2 ; $26 = 4 * IRQ number`
102			`ldw $26,$26,irqsrv ; get addr of service routine`
103			`jalr $26 ; call service routine`
104			`j resume ; resume task if ISR returns`
105
106			`; resume a task`
107			`resume:`
108			`ldw $29,$0,currentStkTop ; setup kernel mode stack`
109			`sub $29,$29,128 ; restore registers`
110			`ldw $2,$29,8`
111			`ldw $3,$29,12`
112			`ldw $4,$29,16`
113			`ldw $5,$29,20`
114			`ldw $6,$29,24`
115			`ldw $7,$29,28`
116			`ldw $8,$29,32`
117			`ldw $9,$29,36`
118			`ldw $10,$29,40`
119			`ldw $11,$29,44`
120			`ldw $12,$29,48`
121			`ldw $13,$29,52`
122			`ldw $14,$29,56`
123			`ldw $15,$29,60`
124			`ldw $16,$29,64`
125			`ldw $17,$29,68`
126			`ldw $18,$29,72`
127			`ldw $19,$29,76`
128			`ldw $20,$29,80`
129			`ldw $21,$29,84`
130			`ldw $22,$29,88`
131			`ldw $23,$29,92`
132			`ldw $24,$29,96`
133			`ldw $25,$29,100`
134			`ldw $26,$29,116 ; this is the task's sp`
135			`ldw $27,$29,4 ; this is the task's $1`
136			`ldw $30,$29,120 ; this is the task's resumption addr`
137			`ldw $31,$29,124`
138			`add $1,$27,$0 ; $27 -> $1`
139			`add $29,$26,$0 ; $26 -> sp`
140			`rfx ; return from exception`
141
142			`start:`
143	102	hellwig	`add $8,$0,0xA8003FFF`
144			`add $9,$0,0xC0000000`
145			`stw $8,$9,0 ; 0xC0000000: j 0xC0010000`
146			`stw $8,$9,4 ; 0xC0000004: j 0xC0010004`
147			`stw $8,$9,8 ; 0xC0000008: j 0xC0010008`
148	18	hellwig	`mvfs $8,0`
149			`or $8,$8,1 << 27 ; let vector point to RAM`
150			`mvts $8,0`
151			`add $10,$0,_bdata ; copy data segment`
152			`add $8,$0,_edata`
153			`sub $9,$8,$10`
154			`add $9,$9,_ecode`
155			`j cpytest`
156			`cpyloop:`
157			`ldw $11,$9,0`
158			`stw $11,$8,0`
159			`cpytest:`
160			`sub $8,$8,4`
161			`sub $9,$9,4`
162			`bgeu $8,$10,cpyloop`
163			`add $8,$0,_bbss ; clear bss`
164			`add $9,$0,_ebss`
165			`j clrtest`
166			`clrloop:`
167			`stw $0,$8,0`
168			`add $8,$8,4`
169			`clrtest:`
170			`bltu $8,$9,clrloop`
171			`ldw $29,$0,task0StkTop ; setup kernel mode stack for task 0`
172			`jal main ; call 'main'`
173			`start1:`
174			`j start1 ; loop`
175
176			`enable:`
177			`mvfs $8,0`
178			`or $8,$8,1 << 23`
179			`mvts $8,0`
180			`jr $31`
181
182			`disable:`
183			`mvfs $8,0`
184			`and $8,$8,~(1 << 23)`
185			`mvts $8,0`
186			`jr $31`
187
188			`orMask:`
189			`mvfs $8,0`
190			`and $4,$4,0x0000FFFF ; use lower 16 bits only`
191			`or $8,$8,$4`
192			`mvts $8,0`
193			`jr $31`
194
195			`andMask:`
196			`mvfs $8,0`
197			`or $4,$4,0xFFFF0000 ; use lower 16 bits only`
198			`and $8,$8,$4`
199			`mvts $8,0`
200			`jr $31`
201
202			`getISR:`
203			`sll $4,$4,2`
204			`ldw $2,$4,irqsrv`
205			`jr $31`
206
207			`setISR:`
208			`sll $4,$4,2`
209			`stw $5,$4,irqsrv`
210			`jr $31`
211
212			`startTask:`
213			`ldw $29,$0,currentStkTop ; setup kernel mode stack`
214			`sub $29,$29,128`
215			`stw $0,$29,0 ; preset registers`
216			`stw $0,$29,4`
217			`stw $0,$29,8`
218			`stw $0,$29,12`
219			`stw $0,$29,16`
220			`stw $0,$29,20`
221			`stw $0,$29,24`
222			`stw $0,$29,28`
223			`stw $0,$29,32`
224			`stw $0,$29,36`
225			`stw $0,$29,40`
226			`stw $0,$29,44`
227			`stw $0,$29,48`
228			`stw $0,$29,52`
229			`stw $0,$29,56`
230			`stw $0,$29,60`
231			`stw $0,$29,64`
232			`stw $0,$29,68`
233			`stw $0,$29,72`
234			`stw $0,$29,76`
235			`stw $0,$29,80`
236			`stw $0,$29,84`
237			`stw $0,$29,88`
238			`stw $0,$29,92`
239			`stw $0,$29,96`
240			`stw $0,$29,100`
241			`stw $0,$29,104`
242			`stw $0,$29,108`
243			`stw $0,$29,112`
244			`add $8,$0,0x80000000`
245			`stw $8,$29,116 ; sp`
246			`stw $0,$29,120 ; task starts at virtual addr 0`
247			`stw $0,$29,124`
248			`mvfs $8,0`
249			`or $8,$8,1 << 25 ; set previous mode to 'user'`
250			`or $8,$8,1 << 22 ; and enable interrupts`
251			`mvts $8,0`
252			`j resume`
253
254			`setTLB:`
255			`mvts $4,1 ; set index`
256			`mvts $5,2 ; set entryHi`
257			`mvts $6,3 ; set entryLo`
258			`tbwi ; write TLB entry at index`
259			`jr $31`
260
261			`.data`
262
263			`; interrupt service routine table`
264
265			`.align 4`
266
267			`irqsrv:`
268			`.word 0 ; 00: terminal 0 transmitter interrupt`
269			`.word 0 ; 01: terminal 0 receiver interrupt`
270			`.word 0 ; 02: terminal 1 transmitter interrupt`
271			`.word 0 ; 03: terminal 1 receiver interrupt`
272			`.word 0 ; 04: keyboard interrupt`
273			`.word 0 ; 05: unused`
274			`.word 0 ; 06: unused`
275			`.word 0 ; 07: unused`
276			`.word 0 ; 08: disk interrupt`
277			`.word 0 ; 09: unused`
278			`.word 0 ; 10: unused`
279			`.word 0 ; 11: unused`
280			`.word 0 ; 12: unused`
281			`.word 0 ; 13: unused`
282	38	hellwig	`.word 0 ; 14: timer 0 interrupt`
283			`.word 0 ; 15: timer 1 interrupt`
284	18	hellwig	`.word 0 ; 16: bus timeout exception`
285			`.word 0 ; 17: illegal instruction exception`
286			`.word 0 ; 18: privileged instruction exception`
287			`.word 0 ; 19: divide instruction exception`
288			`.word 0 ; 20: trap instruction exception`
289			`.word 0 ; 21: TLB miss exception`
290			`.word 0 ; 22: TLB write exception`
291			`.word 0 ; 23: TLB invalid exception`
292			`.word 0 ; 24: illegal address exception`
293			`.word 0 ; 25: privileged address exception`
294			`.word 0 ; 26: unused`
295			`.word 0 ; 27: unused`
296			`.word 0 ; 28: unused`
297			`.word 0 ; 29: unused`
298			`.word 0 ; 30: unused`
299			`.word 0 ; 31: unused`