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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [verilog/] [alu_barrel_shifter.v] - Blame information for rev 6

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// port from univeristy project for an ALU in VHDL
//
module alu_barrel_shifter       (
                            x          ,
                            y          ,
                            z          ,
                            c          ,
                            direction
                                            );
 
  parameter SHIFTER_WIDTH       = 8;
 
  input   [SHIFTER_WIDTH - 1 : 0] x          ;
  input   [SHIFTER_WIDTH - 1 : 0] y          ;
  output  [SHIFTER_WIDTH - 1 : 0] z          ;
  output                          c          ;
  input                           direction  ;
 
 
  wire  [SHIFTER_WIDTH : 0]     Yor       ;
  wire  [SHIFTER_WIDTH : 0]     Yreg      ;
  wire  [SHIFTER_WIDTH : 0]     Xreg      ;
  reg   [SHIFTER_WIDTH : 0]     Zreg      ;
  wire  [SHIFTER_WIDTH : 0]     Zout      ;
 
  wire  [SHIFTER_WIDTH : 0]     Xrev      ;
  wire  [SHIFTER_WIDTH : 0]     Zrev      ;
 
  reg   [SHIFTER_WIDTH-1 : 0]   Zrev_copy ; //  for missing bits
 
  wire                          Xmsb      ;
 
  reg         Ztmp, update_extra_bits;
  integer     j, k, m;
 
  //initial update_extra_bits = 1'b0;
 
 function [SHIFTER_WIDTH : 0] reverse;
 input  [SHIFTER_WIDTH : 0] a         ;
 reg      [0 : SHIFTER_WIDTH] a_reversed;
 reg    [31:0]              i         ;
 begin
         for (i=0;i<= SHIFTER_WIDTH;i = i + 1)
                 a_reversed[i]  = a[i];
         reverse = a_reversed;
 end
 endfunction
 
 
  wire  [SHIFTER_WIDTH : 0]     value_7  ;
 
  assign value_7 = 'h7;
        ////////////////////////////////////////////////////
  // shifter
  ////////////////////////////////////////////////////
 
  ///  theoretical solution for missing bits START ///
  //assign Zrev_copy = {Xreg[SHIFTER_WIDTH-1:SHIFTER_WIDTH-m] ;
  ///  theoretical solution for missing bits END  ///
 
  assign  Yreg  =       {1'b0, y & value_7}                                   ;
        assign  Zrev    =       reverse(Zreg)                                         ;
        assign  Xrev    =       (!direction) ? reverse({1'b0, x}) :     reverse({x, 1'b0});
//      assign  Xmsb    =       x[SHIFTER_WIDTH-1]                                    ;
        assign  Xmsb    =       (y[2:0]==0) ? x[SHIFTER_WIDTH-1] : 1'b0             ;
        //assign  z               =     (!direction) ? Zout[SHIFTER_WIDTH-1:0]  : {Xmsb, Zout[SHIFTER_WIDTH-1:1]} ;
 
        assign  z                 =     (!direction) ? Zout[SHIFTER_WIDTH-1:0]   : {Xmsb, Zout[SHIFTER_WIDTH-1:1]} | ((y[2:0]==0) ? 'd0 : Zrev_copy);
 
        assign  c                 =     (!direction) ? Zout[SHIFTER_WIDTH]          :   Zout[0]                         ;
 
        assign  Zout    =       (!direction) ? Zreg                     : Zrev                            ;
 
        assign  Xreg    = (!direction) ? {1'b0, x}                : Xrev                            ;
 
 
        assign  Yor[0]= (Yreg == 'd0) ? 1'b1 : 1'b0;
        assign  Yor[1]= (Yreg == 'd1) ? 1'b1 : 1'b0;
        assign  Yor[2]= (Yreg == 'd2) ? 1'b1 : 1'b0;
        assign  Yor[3]= (Yreg == 'd3) ? 1'b1 : 1'b0;
        assign  Yor[4]= (Yreg == 'd4) ? 1'b1 : 1'b0;
        assign  Yor[5]= (Yreg == 'd5) ? 1'b1 : 1'b0;
        assign  Yor[6]= (Yreg == 'd6) ? 1'b1 : 1'b0;
        assign  Yor[7]= (Yreg == 'd7) ? 1'b1 : 1'b0;
        assign  Yor[8]= 1'b0;
 
 
  // shifter       :    process (Xreg, Yreg, Yor)
  // temporary variables but declare as regs
  // for synthesis reasons.
  // They extra unneeded bits should be optimized away
  //
  initial j = 'd0;
  initial k = 'd0;
 
  initial update_extra_bits = 1'b0;
 
  always @(x or y or direction)
  begin
    update_extra_bits = 1'b0;
  end
 
  always @(Xreg or Yreg or Yor)
        begin
    //#1;
                Zreg = 'h0;
    `ifdef DEBUG_BARREL_SHIFTER
      $display("**** BARREL SHIFTER always block stage 1 ****");
    `endif
    for (j=SHIFTER_WIDTH; j>=0 ; j=j-1)
    begin
                  Ztmp = 1'b0;
                        if (j == 0)
      begin
                                Zreg[j] =       Xreg[j] & Yor[0];
        `ifdef DEBUG_BARREL_SHIFTER
          $display("**** BARREL SHIFTER always block stage 2 ****");
          $display("%d %d", j, k);
        `endif
      end
                        else
      begin
        `ifdef DEBUG_BARREL_SHIFTER
          $display("**** BARREL SHIFTER always block stage 3 ****");
          $display("%d %d", j, k);
        `endif
                                Ztmp      = Xreg[j] & Yor[0];
                                for (k=1 ; k<=j ; k=k+1)
        begin
                                        Ztmp   =  (Xreg[j-k]  &  Yor[k]) | Ztmp;
 
          if (Yor[k] && direction)
          begin
                        Zrev_copy = 'd0 ;
            for(m=0; m<k ; m=m+1)
            begin
              update_extra_bits = 1'b1;
              Zrev_copy[(SHIFTER_WIDTH-k)+m] = x[m];
        `ifdef DEBUG_BARREL_SHIFTER
              $display("[%0t]Updating Zrev_copy[%d] = %b  Zrev_copy=%b %b %b", $time, m, Zrev_copy[m], Zrev_copy, Xreg, x);
        `endif
            end
          end
        end
      `ifdef DEBUG_BARREL_SHIFTER
        $display("[%0t] Xreg %b Xrev %b x %b", $time, Xreg, Xrev, x);
      `endif
                                Zreg[j] = Ztmp;
                        end // end else
        `ifdef DEBUG_BARREL_SHIFTER
          $display("**** BARREL SHIFTER always block stage LOOP ****");
          $display("%d %d", j, k);
        `endif
                end // end loop
        `ifdef DEBUG_BARREL_SHIFTER
          $display("**** BARREL SHIFTER always block stage END ****");
          $display("%d %d", j, k);
        `endif
        end //end shifter;
 
endmodule

Line No.	Rev	Author	Line
1	5	leonous	`// port from univeristy project for an ALU in VHDL`
2			`//`
3			`module alu_barrel_shifter (`
4			`x ,`
5			`y ,`
6			`z ,`
7			`c ,`
8			`direction`
9			`);`
10
11			`parameter SHIFTER_WIDTH = 8;`
12
13			`input [SHIFTER_WIDTH - 1 : 0] x ;`
14			`input [SHIFTER_WIDTH - 1 : 0] y ;`
15			`output [SHIFTER_WIDTH - 1 : 0] z ;`
16			`output c ;`
17			`input direction ;`
18
19
20			`wire [SHIFTER_WIDTH : 0] Yor ;`
21			`wire [SHIFTER_WIDTH : 0] Yreg ;`
22			`wire [SHIFTER_WIDTH : 0] Xreg ;`
23			`reg [SHIFTER_WIDTH : 0] Zreg ;`
24			`wire [SHIFTER_WIDTH : 0] Zout ;`
25
26			`wire [SHIFTER_WIDTH : 0] Xrev ;`
27			`wire [SHIFTER_WIDTH : 0] Zrev ;`
28
29			`reg [SHIFTER_WIDTH-1 : 0] Zrev_copy ; // for missing bits`
30
31			`wire Xmsb ;`
32
33			`reg Ztmp, update_extra_bits;`
34			`integer j, k, m;`
35
36			`//initial update_extra_bits = 1'b0;`
37
38			`function [SHIFTER_WIDTH : 0] reverse;`
39			`input [SHIFTER_WIDTH : 0] a ;`
40			`reg [0 : SHIFTER_WIDTH] a_reversed;`
41			`reg [31:0] i ;`
42			`begin`
43			`for (i=0;i<= SHIFTER_WIDTH;i = i + 1)`
44			`a_reversed[i] = a[i];`
45			`reverse = a_reversed;`
46			`end`
47			`endfunction`
48
49
50			`wire [SHIFTER_WIDTH : 0] value_7 ;`
51
52			`assign value_7 = 'h7;`
53			`////////////////////////////////////////////////////`
54			`// shifter`
55			`////////////////////////////////////////////////////`
56
57			`/// theoretical solution for missing bits START ///`
58			`//assign Zrev_copy = {Xreg[SHIFTER_WIDTH-1:SHIFTER_WIDTH-m] ;`
59			`/// theoretical solution for missing bits END ///`
60
61			`assign Yreg = {1'b0, y & value_7} ;`
62			`assign Zrev = reverse(Zreg) ;`
63			`assign Xrev = (!direction) ? reverse({1'b0, x}) : reverse({x, 1'b0});`
64			`// assign Xmsb = x[SHIFTER_WIDTH-1] ;`
65			`assign Xmsb = (y[2:0]==0) ? x[SHIFTER_WIDTH-1] : 1'b0 ;`
66			`//assign z = (!direction) ? Zout[SHIFTER_WIDTH-1:0] : {Xmsb, Zout[SHIFTER_WIDTH-1:1]} ;`
67
68			`assign z = (!direction) ? Zout[SHIFTER_WIDTH-1:0] : {Xmsb, Zout[SHIFTER_WIDTH-1:1]} \| ((y[2:0]==0) ? 'd0 : Zrev_copy);`
69
70			`assign c = (!direction) ? Zout[SHIFTER_WIDTH] : Zout[0] ;`
71
72			`assign Zout = (!direction) ? Zreg : Zrev ;`
73
74			`assign Xreg = (!direction) ? {1'b0, x} : Xrev ;`
75
76
77			`assign Yor[0]= (Yreg == 'd0) ? 1'b1 : 1'b0;`
78			`assign Yor[1]= (Yreg == 'd1) ? 1'b1 : 1'b0;`
79			`assign Yor[2]= (Yreg == 'd2) ? 1'b1 : 1'b0;`
80			`assign Yor[3]= (Yreg == 'd3) ? 1'b1 : 1'b0;`
81			`assign Yor[4]= (Yreg == 'd4) ? 1'b1 : 1'b0;`
82			`assign Yor[5]= (Yreg == 'd5) ? 1'b1 : 1'b0;`
83			`assign Yor[6]= (Yreg == 'd6) ? 1'b1 : 1'b0;`
84			`assign Yor[7]= (Yreg == 'd7) ? 1'b1 : 1'b0;`
85			`assign Yor[8]= 1'b0;`
86
87
88			`// shifter : process (Xreg, Yreg, Yor)`
89			`// temporary variables but declare as regs`
90			`// for synthesis reasons.`
91			`// They extra unneeded bits should be optimized away`
92			`//`
93			`initial j = 'd0;`
94			`initial k = 'd0;`
95
96			`initial update_extra_bits = 1'b0;`
97
98			`always @(x or y or direction)`
99			`begin`
100			`update_extra_bits = 1'b0;`
101			`end`
102
103			`always @(Xreg or Yreg or Yor)`
104			`begin`
105			`//#1;`
106			`Zreg = 'h0;`
107			`ifdef DEBUG_BARREL_SHIFTER
108			`$display("** BARREL SHIFTER always block stage 1 **");`
109			`endif
110			`for (j=SHIFTER_WIDTH; j>=0 ; j=j-1)`
111			`begin`
112			`Ztmp = 1'b0;`
113			`if (j == 0)`
114			`begin`
115			`Zreg[j] = Xreg[j] & Yor[0];`
116			`ifdef DEBUG_BARREL_SHIFTER
117			`$display("** BARREL SHIFTER always block stage 2 **");`
118			`$display("%d %d", j, k);`
119			`endif
120			`end`
121			`else`
122			`begin`
123			`ifdef DEBUG_BARREL_SHIFTER
124			`$display("** BARREL SHIFTER always block stage 3 **");`
125			`$display("%d %d", j, k);`
126			`endif
127			`Ztmp = Xreg[j] & Yor[0];`
128			`for (k=1 ; k<=j ; k=k+1)`
129			`begin`
130			`Ztmp = (Xreg[j-k] & Yor[k]) \| Ztmp;`
131
132			`if (Yor[k] && direction)`
133			`begin`
134			`Zrev_copy = 'd0 ;`
135			`for(m=0; m<k ; m=m+1)`
136			`begin`
137			`update_extra_bits = 1'b1;`
138			`Zrev_copy[(SHIFTER_WIDTH-k)+m] = x[m];`
139			`ifdef DEBUG_BARREL_SHIFTER
140			`$display("[%0t]Updating Zrev_copy[%d] = %b Zrev_copy=%b %b %b", $time, m, Zrev_copy[m], Zrev_copy, Xreg, x);`
141			`endif
142			`end`
143			`end`
144			`end`
145			`ifdef DEBUG_BARREL_SHIFTER
146			`$display("[%0t] Xreg %b Xrev %b x %b", $time, Xreg, Xrev, x);`
147			`endif
148			`Zreg[j] = Ztmp;`
149			`end // end else`
150			`ifdef DEBUG_BARREL_SHIFTER
151			`$display("** BARREL SHIFTER always block stage LOOP **");`
152			`$display("%d %d", j, k);`
153			`endif
154			`end // end loop`
155			`ifdef DEBUG_BARREL_SHIFTER
156			`$display("** BARREL SHIFTER always block stage END **");`
157			`$display("%d %d", j, k);`
158			`endif
159			`end //end shifter;`
160
161			`endmodule`

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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [verilog/] [alu_barrel_shifter.v] - Blame information for rev 6