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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [verilog/] [alu_controller.v] - Blame information for rev 5

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// port from university project for ALU in VHDL
// 
`include "alu_controller.vh"
module alu_controller (
                        add_AB          ,
                        inc_A           ,
                        inc_B           ,
                        sub_AB          ,
                        cmp_AB          ,
                        sl_AB           ,
                        sr_AB           ,
                        clr             ,
                        dec_A           ,
                        dec_B           ,
                        mul_AB          ,
                        cpl_A           ,
                        and_AB          ,
                        or_AB           ,
                        xor_AB          ,
                        cpl_B           ,
 
                        clr_Z           ,
                        clr_V           ,
                        clr_C           ,
 
                        load_inputs     ,
                        load_outputs    ,
 
                        opcode          ,
                        reset           ,
                        clk
                       );
 
  // default opcode bit width
  parameter OPWIDTH = 4;
  parameter OPBITS  = 1<<OPWIDTH;
 
  output                    add_AB          ;
  output                    inc_A           ;
  output                    inc_B           ;
  output                    sub_AB          ;
  output                    cmp_AB          ;
  output                    sl_AB           ;
  output                    sr_AB           ;
  output                    clr             ;
  output                    dec_A           ;
  output                    dec_B           ;
  output                    mul_AB          ;
  output                    cpl_A           ;
  output                    and_AB          ;
  output                    or_AB           ;
  output                    xor_AB          ;
  output                    cpl_B           ;
 
  output                    clr_Z           ;
  output                    clr_V           ;
  output                    clr_C           ;
 
  output                    load_inputs     ;
  output                    load_outputs    ;
 
  reg                       load_inputs     ;
  reg                       load_outputs    ;
 
  input    [OPWIDTH-1:0]    opcode          ;
  input                     reset           ;
  input                     clk             ;
 
 
 
  reg    [OPWIDTH-1     :0] this_opcode     ;
  reg    [OPWIDTH-1     :0] next_opcode     ;
 
  reg    [(1<<OPBITS)+1:0]  opcode_sel      ;
 
 
  assign add_AB =   opcode_sel[ `cADD_AB  ];
  assign inc_A  =   opcode_sel[ `cINC_A   ];
  assign inc_B  =   opcode_sel[ `cINC_B   ];
  assign sub_AB =   opcode_sel[ `cSUB_AB  ];
  assign cmp_AB =   opcode_sel[ `cCMP_AB  ];
  assign sl_AB  =   opcode_sel[ `cASL_AbyB];
  assign sr_AB  =   opcode_sel[ `cASR_AbyB];
  assign clr    =   opcode_sel[ `cCLR     ];
  assign dec_A  =   opcode_sel[ `cDEC_A   ];
  assign dec_B  =   opcode_sel[ `cDEC_B   ];
  assign mul_AB =   opcode_sel[ `cMUL_AB  ];
  assign cpl_A  =   opcode_sel[ `cCPL_A   ];
  assign and_AB =   opcode_sel[ `cAND_AB  ];
  assign or_AB  =   opcode_sel[ `cOR_AB   ];
  assign xor_AB =   opcode_sel[ `cXOR_AB  ];
  assign cpl_B  =   opcode_sel[ `cCPL_B   ];
 
  // [leo 22MAR09 TOREVIEW] to be reviewed
  //assign clr_Z  =   opcode_sel[   `clrZ];
  //assign clr_V  =   opcode_sel[   `clrV];
  //assign clr_C  =   opcode_sel[   `clrC];
 
  // state control
  //always @(posedge clk or reset)
  always @(posedge clk or reset) // for systemc
  begin
    if    (reset)
      this_opcode <= `cCLR;
    else
      this_opcode <= opcode;
 
  end
 
  // FSM 
  always @(this_opcode)
  begin
 
    // reset opcode_sel signals
    opcode_sel    <= 'h0;
    load_inputs   <= 'h0;
 
    case (this_opcode)
      `cCLR     :
                        begin
        opcode_sel[`cCLR   ]       <= 1'b1  ;
                        end
      `cADD_AB  :
                        begin
        opcode_sel[`cADD_AB]       <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cINC_A    :
                        begin
 
        opcode_sel[`cINC_A]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cINC_B    :
                        begin
 
        opcode_sel[`cINC_B]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cDEC_A    :
                        begin
 
        opcode_sel[`cDEC_A]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cDEC_B    :
                        begin
 
        opcode_sel[`cDEC_B]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cSUB_AB  :
                        begin
 
        opcode_sel[`cSUB_AB]       <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cCMP_AB  :
                        begin
 
        opcode_sel[`cCMP_AB]       <= 1'b1;
        load_inputs                <= 1'b1;
 
                        end
      `cAND_AB  :
                        begin
 
        opcode_sel[`cAND_AB]       <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cOR_AB    :
                        begin
 
        opcode_sel[`cOR_AB]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cXOR_AB  :
                        begin
 
        opcode_sel[`cXOR_AB]       <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cMUL_AB  :
                        begin
 
        opcode_sel[`cMUL_AB]       <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cCPL_A    :
                        begin
 
        opcode_sel[`cCPL_A]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cCPL_B    :
                        begin
 
        opcode_sel[`cCPL_B]        <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cASL_AbyB  :
                        begin
 
        opcode_sel[`cASL_AbyB]     <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      `cASR_AbyB  :
                        begin
 
        opcode_sel[`cASR_AbyB]     <= 1'b1;
        load_inputs                <= 1'b1;
        load_outputs               <= 1'b1;
 
                        end
      default :
                        begin
        next_opcode       <= this_opcode;
      end
                        endcase
  end // always begin for FSM
endmodule

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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [verilog/] [alu_controller.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	leonous	`// port from university project for ALU in VHDL`
2			`//`
3			`include "alu_controller.vh"
4			`module alu_controller (`
5			`add_AB ,`
6			`inc_A ,`
7			`inc_B ,`
8			`sub_AB ,`
9			`cmp_AB ,`
10			`sl_AB ,`
11			`sr_AB ,`
12			`clr ,`
13			`dec_A ,`
14			`dec_B ,`
15			`mul_AB ,`
16			`cpl_A ,`
17			`and_AB ,`
18			`or_AB ,`
19			`xor_AB ,`
20			`cpl_B ,`
21
22			`clr_Z ,`
23			`clr_V ,`
24			`clr_C ,`
25
26			`load_inputs ,`
27			`load_outputs ,`
28
29			`opcode ,`
30			`reset ,`
31			`clk`
32			`);`
33
34			`// default opcode bit width`
35			`parameter OPWIDTH = 4;`
36			`parameter OPBITS = 1<<OPWIDTH;`
37
38			`output add_AB ;`
39			`output inc_A ;`
40			`output inc_B ;`
41			`output sub_AB ;`
42			`output cmp_AB ;`
43			`output sl_AB ;`
44			`output sr_AB ;`
45			`output clr ;`
46			`output dec_A ;`
47			`output dec_B ;`
48			`output mul_AB ;`
49			`output cpl_A ;`
50			`output and_AB ;`
51			`output or_AB ;`
52			`output xor_AB ;`
53			`output cpl_B ;`
54
55			`output clr_Z ;`
56			`output clr_V ;`
57			`output clr_C ;`
58
59			`output load_inputs ;`
60			`output load_outputs ;`
61
62			`reg load_inputs ;`
63			`reg load_outputs ;`
64
65			`input [OPWIDTH-1:0] opcode ;`
66			`input reset ;`
67			`input clk ;`
68
69
70
71			`reg [OPWIDTH-1 :0] this_opcode ;`
72			`reg [OPWIDTH-1 :0] next_opcode ;`
73
74			`reg [(1<<OPBITS)+1:0] opcode_sel ;`
75
76
77			assign add_AB = opcode_sel[ `cADD_AB ];
78			assign inc_A = opcode_sel[ `cINC_A ];
79			assign inc_B = opcode_sel[ `cINC_B ];
80			assign sub_AB = opcode_sel[ `cSUB_AB ];
81			assign cmp_AB = opcode_sel[ `cCMP_AB ];
82			assign sl_AB = opcode_sel[ `cASL_AbyB];
83			assign sr_AB = opcode_sel[ `cASR_AbyB];
84			assign clr = opcode_sel[ `cCLR ];
85			assign dec_A = opcode_sel[ `cDEC_A ];
86			assign dec_B = opcode_sel[ `cDEC_B ];
87			assign mul_AB = opcode_sel[ `cMUL_AB ];
88			assign cpl_A = opcode_sel[ `cCPL_A ];
89			assign and_AB = opcode_sel[ `cAND_AB ];
90			assign or_AB = opcode_sel[ `cOR_AB ];
91			assign xor_AB = opcode_sel[ `cXOR_AB ];
92			assign cpl_B = opcode_sel[ `cCPL_B ];
93
94			`// [leo 22MAR09 TOREVIEW] to be reviewed`
95			//assign clr_Z = opcode_sel[ `clrZ];
96			//assign clr_V = opcode_sel[ `clrV];
97			//assign clr_C = opcode_sel[ `clrC];
98
99			`// state control`
100			`//always @(posedge clk or reset)`
101			`always @(posedge clk or reset) // for systemc`
102			`begin`
103			`if (reset)`
104			this_opcode <= `cCLR;
105			`else`
106			`this_opcode <= opcode;`
107
108			`end`
109
110			`// FSM`
111			`always @(this_opcode)`
112			`begin`
113
114			`// reset opcode_sel signals`
115			`opcode_sel <= 'h0;`
116			`load_inputs <= 'h0;`
117
118			`case (this_opcode)`
119			`cCLR :
120			`begin`
121			opcode_sel[`cCLR ] <= 1'b1 ;
122			`end`
123			`cADD_AB :
124			`begin`
125			opcode_sel[`cADD_AB] <= 1'b1;
126			`load_inputs <= 1'b1;`
127			`load_outputs <= 1'b1;`
128
129			`end`
130			`cINC_A :
131			`begin`
132
133			opcode_sel[`cINC_A] <= 1'b1;
134			`load_inputs <= 1'b1;`
135			`load_outputs <= 1'b1;`
136
137			`end`
138			`cINC_B :
139			`begin`
140
141			opcode_sel[`cINC_B] <= 1'b1;
142			`load_inputs <= 1'b1;`
143			`load_outputs <= 1'b1;`
144
145			`end`
146			`cDEC_A :
147			`begin`
148
149			opcode_sel[`cDEC_A] <= 1'b1;
150			`load_inputs <= 1'b1;`
151			`load_outputs <= 1'b1;`
152
153			`end`
154			`cDEC_B :
155			`begin`
156
157			opcode_sel[`cDEC_B] <= 1'b1;
158			`load_inputs <= 1'b1;`
159			`load_outputs <= 1'b1;`
160
161			`end`
162			`cSUB_AB :
163			`begin`
164
165			opcode_sel[`cSUB_AB] <= 1'b1;
166			`load_inputs <= 1'b1;`
167			`load_outputs <= 1'b1;`
168
169			`end`
170			`cCMP_AB :
171			`begin`
172
173			opcode_sel[`cCMP_AB] <= 1'b1;
174			`load_inputs <= 1'b1;`
175
176			`end`
177			`cAND_AB :
178			`begin`
179
180			opcode_sel[`cAND_AB] <= 1'b1;
181			`load_inputs <= 1'b1;`
182			`load_outputs <= 1'b1;`
183
184			`end`
185			`cOR_AB :
186			`begin`
187
188			opcode_sel[`cOR_AB] <= 1'b1;
189			`load_inputs <= 1'b1;`
190			`load_outputs <= 1'b1;`
191
192			`end`
193			`cXOR_AB :
194			`begin`
195
196			opcode_sel[`cXOR_AB] <= 1'b1;
197			`load_inputs <= 1'b1;`
198			`load_outputs <= 1'b1;`
199
200			`end`
201			`cMUL_AB :
202			`begin`
203
204			opcode_sel[`cMUL_AB] <= 1'b1;
205			`load_inputs <= 1'b1;`
206			`load_outputs <= 1'b1;`
207
208			`end`
209			`cCPL_A :
210			`begin`
211
212			opcode_sel[`cCPL_A] <= 1'b1;
213			`load_inputs <= 1'b1;`
214			`load_outputs <= 1'b1;`
215
216			`end`
217			`cCPL_B :
218			`begin`
219
220			opcode_sel[`cCPL_B] <= 1'b1;
221			`load_inputs <= 1'b1;`
222			`load_outputs <= 1'b1;`
223
224			`end`
225			`cASL_AbyB :
226			`begin`
227
228			opcode_sel[`cASL_AbyB] <= 1'b1;
229			`load_inputs <= 1'b1;`
230			`load_outputs <= 1'b1;`
231
232			`end`
233			`cASR_AbyB :
234			`begin`
235
236			opcode_sel[`cASR_AbyB] <= 1'b1;
237			`load_inputs <= 1'b1;`
238			`load_outputs <= 1'b1;`
239
240			`end`
241			`default :`
242			`begin`
243			`next_opcode <= this_opcode;`
244			`end`
245			`endcase`
246			`end // always begin for FSM`
247			`endmodule`