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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [verilog/] [alu_controller.vh] - Blame information for rev 5

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Line No. Rev Author Line
1 5 leonous 
// alu controller defines
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// `define  addAB     00
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// `define  subAB     01
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// `define  incA      02
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// `define  incB      03
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// `define  decA      04
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// `define  decB      05
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// `define  cmpAB     06
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// `define  andAB     07
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// `define  orAB      08
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// `define  xorAB     09
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// `define  cplB      10
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// `define  cplA      11
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// `define  slAB      12
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// `define  srAB      13
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// `define  clrALL    14
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`define  clrZ       0
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`define  clrV       1
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`define  clrC       2
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`define  cADD_AB    0
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`define  cINC_A     1
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`define  cINC_B     9
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`define  cSUB_AB    2
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`define  cCMP_AB    3
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`define  cASL_AbyB  4
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`define  cASR_AbyB  5
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`define  cCLR       6
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`define  cDEC_A     7
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`define  cDEC_B     8
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`define  cMUL_AB   10
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`define  cCPL_A    11
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`define  cAND_AB   12
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`define  cOR_AB    13
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`define  cXOR_AB   14
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`define  cCPL_B    15

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