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--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Module   - Introduction to VLSI Design [03ELD005]
-- Lecturer - Dr V. M. Dwyer
-- Course   - MEng Electronic and Electrical Engineering
-- Year     - Part D
-- Student  - Sahrfili Leonous Matturi A028459 [elslm]
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Final coursework 2004
-- 
-- Details:     Design and Layout of an ALU
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
 
--      Description     :       ALU controller
--  Entity                      :       alu_controller
--      Architecture    :       behavioural
--  Created on          :       07/03/2004
 
library ieee;
 
use ieee.std_logic_1164.all;
use     ieee.std_logic_unsigned.all;
 
entity alu is
        port    (
                        A                       : in    std_logic_vector(7 downto 0);
                        B                       : in    std_logic_vector(7 downto 0);
                        S                       : in    std_logic_vector(3 downto 0);
                        Y                       : out   std_logic_vector(7 downto 0);
                        CLR             : in    std_logic                                       ;
                        CLK                     : in    std_logic                                       ;
                        C                       : out   std_logic                                       ;
                        V                       : out   std_logic                                       ;
                        Z                       : out   std_logic
                        );
end alu;
 
architecture structural of alu is
component alu_controller
        port    (
                        add_AB          : out   std_logic;
                        sub_AB          : out   std_logic;
                        inc_A           : out   std_logic;
                        inc_B           : out   std_logic;
                        dec_A           : out   std_logic;
                        dec_B           : out   std_logic;
                        cmp_AB          : out   std_logic;
                        and_AB          : out   std_logic;
                        or_AB           : out   std_logic;
                        xor_AB          : out   std_logic;
                        cpl_B           : out   std_logic;
                        cpl_A           : out   std_logic;
                        sl_AB           : out   std_logic;
                        sr_AB           : out   std_logic;
                        clr                     : out   std_logic;
 
                        clr_Z           : out   std_logic;
                        clr_V           : out   std_logic;
                        clr_C           : out   std_logic;
 
                        load_inputs     : out   std_logic;
                        load_outputs: out       std_logic;
 
 
                        opcode          : in    std_logic_vector(3 downto 0);
                        reset           : in    std_logic;
                        clk                     : in    std_logic
                        );
end component;
component alu_datapath
        port    (
                        A                       : in    std_logic_vector(7 downto 0);
                        B                       : in    std_logic_vector(7 downto 0);
                        Y                       : out   std_logic_vector(7 downto 0);
 
                        add_AB          : in    std_logic;
                        sub_AB          : in    std_logic;
                        inc_A           : in    std_logic;
                        inc_B           : in    std_logic;
                        dec_A           : in    std_logic;
                        dec_B           : in    std_logic;
                        cmp_AB          : in    std_logic;
                        and_AB          : in    std_logic;
                        or_AB           : in    std_logic;
                        xor_AB          : in    std_logic;
                        cpl_B           : in    std_logic;
                        cpl_A           : in    std_logic;
                        sl_AB           : in    std_logic;
                        sr_AB           : in    std_logic;
                        clr                     : in    std_logic;
 
                        clr_Z           : in    std_logic;
                        clr_V           : in    std_logic;
                        clr_C           : in    std_logic;
 
                        C                       : out   std_logic;
                        V                       : out   std_logic;
                        Z                       : out   std_logic;
 
                        load_inputs     : in    std_logic;
                        load_outputs: in        std_logic;
 
                        reset           : in    std_logic;
 
                        clk                     : in    std_logic
                        );
end component;
 
signal                                  add_AB          :       std_logic                                       ;
signal                                  sub_AB          :       std_logic                                       ;
signal                                  inc_A           :       std_logic                                       ;
signal                                  inc_B           :       std_logic                                       ;
signal                                  dec_A           :       std_logic                                       ;
signal                                  dec_B           :       std_logic                                       ;
signal                                  cmp_AB          :       std_logic                                       ;
signal                                  and_AB          :       std_logic                                       ;
signal                                  or_AB           :       std_logic                                       ;
signal                                  xor_AB          :       std_logic                                       ;
signal                                  cpl_B           :       std_logic                                       ;
signal                                  cpl_A           :       std_logic                                       ;
signal                                  sl_AB           :       std_logic                                       ;
signal                                  sr_AB           :       std_logic                                       ;
signal                                  clr_ALL         :       std_logic                                       ;
 
signal                                  clr_Z           :       std_logic                                       ;
signal                                  clr_V           :       std_logic                                       ;
signal                                  clr_C           :       std_logic                                       ;
 
signal                                  reset           :       std_logic                                       ;
signal                                  load_inputs     :       std_logic                                       ;
signal                                  load_outputs:   std_logic                                       ;
 
begin
        -- clear is the same as reset
        reset   <=      CLR;
 
        controller      :       alu_controller
                port map        (
                                        add_AB          ,
                                        sub_AB          ,
                                        inc_A           ,
                                        inc_B           ,
                                        dec_A           ,
                                        dec_B           ,
                                        cmp_AB          ,
                                        and_AB          ,
                                        or_AB           ,
                                        xor_AB          ,
                                        cpl_B           ,
                                        cpl_A           ,
                                        sl_AB           ,
                                        sr_AB           ,
                                        clr_ALL         ,
 
                                        clr_Z           ,
                                        clr_V           ,
                                        clr_C           ,
 
                                        load_inputs     ,
                                        load_outputs,
 
                                        S                       ,
 
                                        reset           ,
                                        clk
                                        );
        datapath        :       alu_datapath
                port map        (
                                        A                       ,
                                        B                       ,
                                        Y                       ,
 
                                        add_AB          ,
                                        sub_AB          ,
                                        inc_A           ,
                                        inc_B           ,
                                        dec_A           ,
                                        dec_B           ,
                                        cmp_AB          ,
                                        and_AB          ,
                                        or_AB           ,
                                        xor_AB          ,
                                        cpl_B           ,
                                        cpl_A           ,
                                        sl_AB           ,
                                        sr_AB           ,
                                        clr_ALL         ,
 
                                        clr_Z           ,
                                        clr_V           ,
                                        clr_C           ,
 
                                        C                       ,
                                        V                       ,
                                        Z                       ,
 
                                        load_inputs     ,
                                        load_outputs,
 
                                        reset,
 
                                        clk
                                        );
end structural;

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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [vhdl/] [alu.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	leonous	`--------------------------------------------------------------------------------`
2			`--------------------------------------------------------------------------------`
3			`-- Module - Introduction to VLSI Design [03ELD005]`
4			`-- Lecturer - Dr V. M. Dwyer`
5			`-- Course - MEng Electronic and Electrical Engineering`
6			`-- Year - Part D`
7			`-- Student - Sahrfili Leonous Matturi A028459 [elslm]`
8			`--------------------------------------------------------------------------------`
9			`--------------------------------------------------------------------------------`
10			`-- Final coursework 2004`
11			`--`
12			`-- Details: Design and Layout of an ALU`
13			`--------------------------------------------------------------------------------`
14			`--------------------------------------------------------------------------------`
15
16			`-- Description : ALU controller`
17			`-- Entity : alu_controller`
18			`-- Architecture : behavioural`
19			`-- Created on : 07/03/2004`
20
21			`library ieee;`
22
23			`use ieee.std_logic_1164.all;`
24			`use ieee.std_logic_unsigned.all;`
25
26			`entity alu is`
27			`port (`
28			`A : in std_logic_vector(7 downto 0);`
29			`B : in std_logic_vector(7 downto 0);`
30			`S : in std_logic_vector(3 downto 0);`
31			`Y : out std_logic_vector(7 downto 0);`
32			`CLR : in std_logic ;`
33			`CLK : in std_logic ;`
34			`C : out std_logic ;`
35			`V : out std_logic ;`
36			`Z : out std_logic`
37			`);`
38			`end alu;`
39
40			`architecture structural of alu is`
41			`component alu_controller`
42			`port (`
43			`add_AB : out std_logic;`
44			`sub_AB : out std_logic;`
45			`inc_A : out std_logic;`
46			`inc_B : out std_logic;`
47			`dec_A : out std_logic;`
48			`dec_B : out std_logic;`
49			`cmp_AB : out std_logic;`
50			`and_AB : out std_logic;`
51			`or_AB : out std_logic;`
52			`xor_AB : out std_logic;`
53			`cpl_B : out std_logic;`
54			`cpl_A : out std_logic;`
55			`sl_AB : out std_logic;`
56			`sr_AB : out std_logic;`
57			`clr : out std_logic;`
58
59			`clr_Z : out std_logic;`
60			`clr_V : out std_logic;`
61			`clr_C : out std_logic;`
62
63			`load_inputs : out std_logic;`
64			`load_outputs: out std_logic;`
65
66
67			`opcode : in std_logic_vector(3 downto 0);`
68			`reset : in std_logic;`
69			`clk : in std_logic`
70			`);`
71			`end component;`
72			`component alu_datapath`
73			`port (`
74			`A : in std_logic_vector(7 downto 0);`
75			`B : in std_logic_vector(7 downto 0);`
76			`Y : out std_logic_vector(7 downto 0);`
77
78			`add_AB : in std_logic;`
79			`sub_AB : in std_logic;`
80			`inc_A : in std_logic;`
81			`inc_B : in std_logic;`
82			`dec_A : in std_logic;`
83			`dec_B : in std_logic;`
84			`cmp_AB : in std_logic;`
85			`and_AB : in std_logic;`
86			`or_AB : in std_logic;`
87			`xor_AB : in std_logic;`
88			`cpl_B : in std_logic;`
89			`cpl_A : in std_logic;`
90			`sl_AB : in std_logic;`
91			`sr_AB : in std_logic;`
92			`clr : in std_logic;`
93
94			`clr_Z : in std_logic;`
95			`clr_V : in std_logic;`
96			`clr_C : in std_logic;`
97
98			`C : out std_logic;`
99			`V : out std_logic;`
100			`Z : out std_logic;`
101
102			`load_inputs : in std_logic;`
103			`load_outputs: in std_logic;`
104
105			`reset : in std_logic;`
106
107			`clk : in std_logic`
108			`);`
109			`end component;`
110
111			`signal add_AB : std_logic ;`
112			`signal sub_AB : std_logic ;`
113			`signal inc_A : std_logic ;`
114			`signal inc_B : std_logic ;`
115			`signal dec_A : std_logic ;`
116			`signal dec_B : std_logic ;`
117			`signal cmp_AB : std_logic ;`
118			`signal and_AB : std_logic ;`
119			`signal or_AB : std_logic ;`
120			`signal xor_AB : std_logic ;`
121			`signal cpl_B : std_logic ;`
122			`signal cpl_A : std_logic ;`
123			`signal sl_AB : std_logic ;`
124			`signal sr_AB : std_logic ;`
125			`signal clr_ALL : std_logic ;`
126
127			`signal clr_Z : std_logic ;`
128			`signal clr_V : std_logic ;`
129			`signal clr_C : std_logic ;`
130
131			`signal reset : std_logic ;`
132			`signal load_inputs : std_logic ;`
133			`signal load_outputs: std_logic ;`
134
135			`begin`
136			`-- clear is the same as reset`
137			`reset <= CLR;`
138
139			`controller : alu_controller`
140			`port map (`
141			`add_AB ,`
142			`sub_AB ,`
143			`inc_A ,`
144			`inc_B ,`
145			`dec_A ,`
146			`dec_B ,`
147			`cmp_AB ,`
148			`and_AB ,`
149			`or_AB ,`
150			`xor_AB ,`
151			`cpl_B ,`
152			`cpl_A ,`
153			`sl_AB ,`
154			`sr_AB ,`
155			`clr_ALL ,`
156
157			`clr_Z ,`
158			`clr_V ,`
159			`clr_C ,`
160
161			`load_inputs ,`
162			`load_outputs,`
163
164			`S ,`
165
166			`reset ,`
167			`clk`
168			`);`
169			`datapath : alu_datapath`
170			`port map (`
171			`A ,`
172			`B ,`
173			`Y ,`
174
175			`add_AB ,`
176			`sub_AB ,`
177			`inc_A ,`
178			`inc_B ,`
179			`dec_A ,`
180			`dec_B ,`
181			`cmp_AB ,`
182			`and_AB ,`
183			`or_AB ,`
184			`xor_AB ,`
185			`cpl_B ,`
186			`cpl_A ,`
187			`sl_AB ,`
188			`sr_AB ,`
189			`clr_ALL ,`
190
191			`clr_Z ,`
192			`clr_V ,`
193			`clr_C ,`
194
195			`C ,`
196			`V ,`
197			`Z ,`
198
199			`load_inputs ,`
200			`load_outputs,`
201
202			`reset,`
203
204			`clk`
205			`);`
206			`end structural;`