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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [vhdl/] [alu_analog_cadence_tb.vhd] - Blame information for rev 5

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1 5 leonous 
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-- Module   - Introduction to VLSI Design [03ELD005]
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-- Lecturer - Dr V. M. Dwyer
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-- Course   - MEng Electronic and Electrical Engineering
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-- Year     - Part D
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-- Student  - Sahrfili Leonous Matturi A028459 [elslm]
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Final coursework 2004
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--
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-- Details:     Design and Layout of an ALU
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--      Description     :       ALU testbench
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--  Entity                      :       alu_tb
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--      Architecture    :       behavioural
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--  Created on          :       07/03/2004
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library ieee;
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use ieee.std_logic_1164.all;
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--use   ieee.std_logic_unsigned.all;
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--use ieee.std_logic_arith.all;                 -- for unsigned()
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-- use std.textio.all;                                  -- for file i/o
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-- use work.txt_util.all;                               -- for string<->other types conversions
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entity alu_analog_cadence_tb is
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    port    (
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                        clock_tb                        : in    std_logic
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            );
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end alu_analog_cadence_tb;
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architecture behavioural of alu_analog_cadence_tb is
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component alu
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        port    (
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                        A                       : in    std_logic_vector(7 downto 0);
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                        B                       : in    std_logic_vector(7 downto 0);
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                        S                       : in    std_logic_vector(3 downto 0);
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                        Y                       : out   std_logic_vector(7 downto 0);
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                        reset           : in    std_logic                                       ;
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                        CLK                     : in    std_logic                                       ;
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                        C                       : out   std_logic                                       ;
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                        V                       : out   std_logic                                       ;
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                        Z                       : out   std_logic
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                        );
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end component;
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-- ALU test vector record
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--      records to store stimulus for verification
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-- ALU access signals
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signal                  A                       : std_logic_vector(7 downto 0)   ;
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signal                  B                       : std_logic_vector(7 downto 0)   ;
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signal                  S                       : std_logic_vector(3 downto 0)   ;
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signal                  Y                       : std_logic_vector(7 downto 0)   ;
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signal                  CLR                     : std_logic                                             ;
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signal                  CLK                     : std_logic                                             ;
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signal                  C                       : std_logic                                             ;
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signal                  V                       : std_logic                                             ;
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signal                  Z                       : std_logic                                             ;
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-- signal                       clock_tb                        : std_logic                                             ;
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--
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-- -- finished = '1' indicates end of test run
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--
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-- -- testbench clock half period
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-- constant     clock_tb_HALF_PERIOD    : time  := 10 ns                                ;
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constant        zero                    : std_logic_vector(7 downto 0)
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                                                                        := (others => '0');
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signal  finished :std_logic;
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-- procedure to write a string to the screen
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-- procedure writestr (s : string) is
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--      variable lout : line;
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--      begin
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--              write(lout, s);
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--              writeline(output, lout);
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--      end writestr;
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--
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-- -- procedure to write a character to the screen
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-- procedure writechr (s : character) is
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--      variable lout : line;
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--      begin
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--              write(lout, s);
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--              writeline(output, lout);
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--      end writechr;
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--
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type out_vector is record
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      A           : std_logic_vector(8 downto 1)    ;
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      B           : std_logic_vector(8 downto 1)    ;
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      S           : std_logic_vector(4 downto 1)    ;
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      Y           : std_logic_vector(8 downto 1)    ;
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      CLR         : std_logic                       ;
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      CLK         : std_logic                       ;
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      C           : std_logic                       ;
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      V           : std_logic                       ;
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      Z           : std_logic                       ;
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 end record;
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type out_vectors is array (natural range <>) of out_vector;
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constant vectors  : out_vectors :=  (
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("UUUUUUUU", "UUUUUUUU", "UUUU", "UUUUUUUU", '1', '1', 'U', 'U', 'U'),
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("01010101", "00000001", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000010", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01011001", '0', '1', '0', '0', '0'),
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("01010101", "00001000", "0000", "01011001", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00010000", "0000", "01011101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00100000", "0000", "01100101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "01000000", "0000", "01110101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0000", "10010101", '0', '1', '0', '0', '0'),
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("01010101", "00000001", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0010", "11010101", '0', '1', '0', '0', '0'),
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("01010101", "00000010", "0010", "01010100", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0010", "01010011", '0', '1', '0', '0', '0'),
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("01010101", "00010000", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "01000000", "0010", "01010001", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0010", "01000101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
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("01010101", "00000001", "0100", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0100", "11010101", '0', '1', '0', '0', '0'),
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("01010101", "00000010", "0101", "10101010", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0101", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0100", "00010101", '0', '1', '0', '0', '0'),
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("01010101", "00010000", "0101", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "01000000", "0010", "01010000", '0', '1', '1', '0', '0'),
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("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0010", "01010101", '0', '1', '0', '0', '0'));
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begin
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        -- instantiate ALU
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        alu_inst0       :       alu
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                port map        (
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                                        A                       ,
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                                        B                       ,
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                                        S                       ,
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                                        Y                       ,
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                                        CLR                     ,
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                                        CLK                     ,
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                                        C                       ,
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                                        V                       ,
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                                        Z
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                                        );
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        -- apply clock stimulus
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--      clock_stim      :       process
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--                                      begin
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--                                              clock_tb        <= '1', '0' after clock_tb_HALF_PERIOD;
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--
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--                                              if (finished /= '1') then
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--                                                      wait for 2 * clock_tb_HALF_PERIOD;
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--                                              else
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--                                                      wait; -- end test
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--                                              end if;
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--                                      end process clock_stim;
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    vector_stim_in : process ( clock_tb )
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                    variable i  : integer := 0;
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                 begin
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                    if (clock_tb'event and clock_tb = '1') then
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                        if ( i <= vectors'high) then
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                            A <= vectors(i).A;
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                            B <= vectors(i).B;
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                            S <= vectors(i).S;
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                            --Y <= vectors(i).Y;
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                            CLR <= vectors(i).CLR;
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                            CLK <= vectors(i).CLK;
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                            --C <= vectors(i).C;
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                            --V <= vectors(i).V;
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                            --Z <= vectors(i).Z;
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                            i := i + 1;
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                        else
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                            finished <= '1';
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                        end if;
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                    else
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                        CLK <= clock_tb;
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                    end if;
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                end process vector_stim_in;
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end behavioural;
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