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----------------------------------------------------------------------------
----                                                                    ----
---- WISHBONE RISCMCU IP Core                                           ----
----                                                                    ----
---- This file is part of the RISCMCU project                           ----
---- http://www.opencores.org/projects/riscmcu/                         ----
----                                                                    ----
---- Description                                                        ----
---- Implementation of a RISC Microcontroller based on Atmel AVR        ----
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
----                                                                    ----
---- Author(s):                                                         ----
----    - Yap Zi He, yapzihe@hotmail.com                                ----
----                                                                    ----
----------------------------------------------------------------------------
----                                                                    ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG                       ----
----                                                                    ----
---- This source file may be used and distributed without               ----
---- restriction provided that this copyright statement is not          ----
---- removed from the file and that any derivative work contains        ----
---- the original copyright notice and the associated disclaimer.       ----
----                                                                    ----
---- This source file is free software; you can redistribute it         ----
---- and/or modify it under the terms of the GNU Lesser General         ----
---- Public License as published by the Free Software Foundation;       ----
---- either version 2.1 of the License, or (at your option) any         ----
---- later version.                                                     ----
----                                                                    ----
---- This source is distributed in the hope that it will be             ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
---- PURPOSE. See the GNU Lesser General Public License for more        ----
---- details.                                                           ----
----                                                                    ----
---- You should have received a copy of the GNU Lesser General          ----
---- Public License along with this source; if not, download it         ----
---- from http://www.opencores.org/lgpl.shtml                           ----
----                                                                    ----
----------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;
 
entity v_alu is
 port(  reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
                c2a, c2b : in std_logic;
                asel : in integer range 0 to 1;
                bsel : in integer range 0 to 3;
 
                bitsel : in integer range 0 to 7;
                set : in std_logic;
                c_flag, t_flag : in std_logic;
 
                add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;
                cpse, skiptest : in std_logic;
 
                wcarry : in std_logic;
                logicsel : in integer range 0 to 3;
                rightsel : in integer range 0 to 2;
                dirsel : in integer range 0 to 1;
 
                clk, clrn : in std_logic;
 
                c : buffer std_logic_vector(7 downto 0);
                tosr : buffer std_logic_vector (6 downto 0);
                skip : out std_logic
 );
 
end v_alu;
 
architecture alu of v_alu is
 
signal a, b : std_logic_vector(7 downto 0);
 
signal sr : std_logic_vector(6 downto 0);
 
signal cin, overflow, cout : std_logic;
 
signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0);
 
begin
 
-- Operand Fetch Unit --
 
process(clrn, clk)
begin
        if clrn = '0' then
                a <= "00000000";
                b <= "00000000";
        elsif clk'event and clk = '1' then
                case asel is
                        when 0 =>
                                if c2a = '1' then
                                        a <= c;
                                else
                                        a <= reg_rd;
                                end if;
                        when 1 =>
                                a <= "00000000";
                end case;
 
                case bsel is
                        when 0 =>
                                if c2b = '1' then
                                        b <= c;
                                else
                                        b <= reg_rr;
                                end if;
                        when 1 =>
                                b <= reg_rd;
                        when 2 =>
                                b <= imm_value;
                        when 3 =>
                                b <= "00000001";
                end case;
        end if;
end process;
 
 
-- Execution Unit --
 
cin <= c_flag when add = '1' and wcarry = '1' else
                '0' when add = '1' and wcarry = '0' else
                not c_flag when wcarry = '1' else
                '1';
 
 
-- Adder-Subtracter
adder1 : lpm_add_sub
        generic map(lpm_width => 8)
        port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);
 
-- Logic Unit
with logicsel select
        logic_out <= a and --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Module   - Introduction to VLSI Design
-- Lecturer - Dr V. M. Dwyer
-- Course   - MEng Electronic and Electrical Engineering
-- Year     - Part D
-- Student  - Sahrfili Leonous Matturi A028459 [elslm]
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Christmas 2003 coursework...
--      better than watching "Saved by the Bell- the college years"
-- Details:     Scheduling and allocation in FSMs
--                              4 bit multiplier design example
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
 
--      Description     :       radix-4 multiplier top level linkink
--                                              datapath and controller
--  Entity                      :       radix4_multi_structure
--      Architecture    :       structural
--  Created on          :       01/01/2004
 
library ieee;
 
use ieee.std_logic_1164.all;
use     ieee.std_logic_unsigned.all;
 
b when 0, -- and, andi
                                a or b when 1, -- or, ori
                                a xor b when 2, -- eor
                                not a when 3; -- com
 
-- Shifter
right_out(6 downto 0) <= a(7 downto 1);
with rightsel select
        right_out(7) <= '0' when 0, -- lsr
                                        c_flag when 1, -- ror
                                        a(7) when 2; -- asr
 
-- Direct Unit
with dirsel select
        dir_out <= b when 0, -- ldi, mov
                                (a(3 downto 0) & a(7 downto 4)) when 1; -- swap
 
-- Bit Loader
process(bld, bitsel, a, t_flag, set)
begin
        for i in 0 to 7 loop
                if i /= bitsel then
                        bldcbi_out(i) <= a(i);
                elsif bld = '1' then
                        bldcbi_out(i) <= t_flag;
                else
                        bldcbi_out(i) <= set;
                end if;
        end loop;
end process;
 
-- Results to Data Bus
process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)
begin
 
 c <= "ZZZZZZZZ";
 
 -- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg
 if add = '1' or subcp = '1' then
        c <= sum;
 end if;
 
 -- and, andi, or, ori, eor, com
 if logic = '1' then
        c <= logic_out;
 end if;
 
 -- lsr, lsr, asr
 if right = '1' then
        c <= right_out;
 end if;
 
 -- ldi, mov, swap
 if dir = '1' then
        c <= dir_out;
 end if;
 
 -- bld, cbisbi
 if bld = '1' or cbisbi = '1' then
        c <= bldcbi_out;
 end if;
 
 -- out, st z, st z+, st -z
 if pass_a = '1' then
        c <= a;
 end if;
 
end process;
 
 
-- Skip Evaluation Unit --
process(cpse, skiptest, a, b, set, bitsel, c)
begin
 
 skip <= '0';
 
 -- cpse
 if cpse = '1' then
        if a = b then
                skip <= '1';
        end if;
 
 -- sbrc, sbrs
 elsif skiptest = '1' then
        if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then
                skip <= '1';
        end if;
 
 end if;
end process;
 
-- Flags Evaluation Unit --
process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)
begin
 
-- C sr(0)
 if add = '1' then
        sr(0) <= cout;
 elsif right = '1' then
        sr(0) <= a(0);
 elsif logic = '1' then -- com
        sr(0) <= '1';
 else -- subcp
        sr(0) <= not cout;
        --sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7));
 end if;
 
-- Z sr(1)
 if (add = '1' or subcp = '1') and sum = "00000000" then
        sr(1) <= '1';
 elsif logic = '1' and logic_out = "00000000" then
        sr(1) <= '1';
 elsif right = '1' and right_out = "00000000" then
        sr(1) <= '1';
 else
        sr(1) <= '0';
 end if;
 
-- N sr(2)
 if (add = '1' or subcp = '1') and sum(7) = '1' then
        sr(2) <= '1';
 elsif logic = '1' and logic_out(7) = '1' then
        sr(2) <= '1';
 elsif right = '1' and right_out(7) = '1' then
        sr(2) <= '1';
 else
        sr(2) <= '0';
 end if;
 
-- V sr(3)
 if right = '1' then
        sr(3) <= right_out(7) xor a(0);
 elsif logic = '1' then
        sr(3) <= '0';
 else
        sr(3) <= overflow;
 end if;
 
-- S sr(4)
 sr(4) <= sr(2) xor sr(3);
 
-- H sr(5)
 if add = '1' then
        sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3));
 else -- subcp
        sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3));
 end if;
 
-- T sr(6)
 sr(6) <= a(bitsel);
 
end process;
 
tosr <= sr;
 
end alu;
 
 
 

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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [vhdl/] [alu_from_net.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	leonous	`----------------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE RISCMCU IP Core ----`
4			`---- ----`
5			`---- This file is part of the RISCMCU project ----`
6			`---- http://www.opencores.org/projects/riscmcu/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Implementation of a RISC Microcontroller based on Atmel AVR ----`
10			`---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----`
11			`---- ----`
12			`---- Author(s): ----`
13			`---- - Yap Zi He, yapzihe@hotmail.com ----`
14			`---- ----`
15			`----------------------------------------------------------------------------`
16			`---- ----`
17			`---- Copyright (C) 2001 Authors and OPENCORES.ORG ----`
18			`---- ----`
19			`---- This source file may be used and distributed without ----`
20			`---- restriction provided that this copyright statement is not ----`
21			`---- removed from the file and that any derivative work contains ----`
22			`---- the original copyright notice and the associated disclaimer. ----`
23			`---- ----`
24			`---- This source file is free software; you can redistribute it ----`
25			`---- and/or modify it under the terms of the GNU Lesser General ----`
26			`---- Public License as published by the Free Software Foundation; ----`
27			`---- either version 2.1 of the License, or (at your option) any ----`
28			`---- later version. ----`
29			`---- ----`
30			`---- This source is distributed in the hope that it will be ----`
31			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
32			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
33			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
34			`---- details. ----`
35			`---- ----`
36			`---- You should have received a copy of the GNU Lesser General ----`
37			`---- Public License along with this source; if not, download it ----`
38			`---- from http://www.opencores.org/lgpl.shtml ----`
39			`---- ----`
40			`----------------------------------------------------------------------------`
41
42			`library ieee;`
43			`use ieee.std_logic_1164.all;`
44			`use ieee.std_logic_arith.all;`
45			`use ieee.std_logic_unsigned.all;`
46			`library lpm;`
47			`use lpm.lpm_components.all;`
48
49			`entity v_alu is`
50			`port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);`
51			`c2a, c2b : in std_logic;`
52			`asel : in integer range 0 to 1;`
53			`bsel : in integer range 0 to 3;`
54
55			`bitsel : in integer range 0 to 7;`
56			`set : in std_logic;`
57			`c_flag, t_flag : in std_logic;`
58
59			`add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;`
60			`cpse, skiptest : in std_logic;`
61
62			`wcarry : in std_logic;`
63			`logicsel : in integer range 0 to 3;`
64			`rightsel : in integer range 0 to 2;`
65			`dirsel : in integer range 0 to 1;`
66
67			`clk, clrn : in std_logic;`
68
69			`c : buffer std_logic_vector(7 downto 0);`
70			`tosr : buffer std_logic_vector (6 downto 0);`
71			`skip : out std_logic`
72			`);`
73
74			`end v_alu;`
75
76			`architecture alu of v_alu is`
77
78			`signal a, b : std_logic_vector(7 downto 0);`
79
80			`signal sr : std_logic_vector(6 downto 0);`
81
82			`signal cin, overflow, cout : std_logic;`
83
84			`signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0);`
85
86			`begin`
87
88			`-- Operand Fetch Unit --`
89
90			`process(clrn, clk)`
91			`begin`
92			`if clrn = '0' then`
93			`a <= "00000000";`
94			`b <= "00000000";`
95			`elsif clk'event and clk = '1' then`
96			`case asel is`
97			`when 0 =>`
98			`if c2a = '1' then`
99			`a <= c;`
100			`else`
101			`a <= reg_rd;`
102			`end if;`
103			`when 1 =>`
104			`a <= "00000000";`
105			`end case;`
106
107			`case bsel is`
108			`when 0 =>`
109			`if c2b = '1' then`
110			`b <= c;`
111			`else`
112			`b <= reg_rr;`
113			`end if;`
114			`when 1 =>`
115			`b <= reg_rd;`
116			`when 2 =>`
117			`b <= imm_value;`
118			`when 3 =>`
119			`b <= "00000001";`
120			`end case;`
121			`end if;`
122			`end process;`
123
124
125			`-- Execution Unit --`
126
127			`cin <= c_flag when add = '1' and wcarry = '1' else`
128			`'0' when add = '1' and wcarry = '0' else`
129			`not c_flag when wcarry = '1' else`
130			`'1';`
131
132
133			`-- Adder-Subtracter`
134			`adder1 : lpm_add_sub`
135			`generic map(lpm_width => 8)`
136			`port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);`
137
138			`-- Logic Unit`
139			`with logicsel select`
140			`logic_out <= a and --------------------------------------------------------------------------------`
141			`--------------------------------------------------------------------------------`
142			`-- Module - Introduction to VLSI Design`
143			`-- Lecturer - Dr V. M. Dwyer`
144			`-- Course - MEng Electronic and Electrical Engineering`
145			`-- Year - Part D`
146			`-- Student - Sahrfili Leonous Matturi A028459 [elslm]`
147			`--------------------------------------------------------------------------------`
148			`--------------------------------------------------------------------------------`
149			`-- Christmas 2003 coursework...`
150			`-- better than watching "Saved by the Bell- the college years"`
151			`-- Details: Scheduling and allocation in FSMs`
152			`-- 4 bit multiplier design example`
153			`--------------------------------------------------------------------------------`
154			`--------------------------------------------------------------------------------`
155
156			`-- Description : radix-4 multiplier top level linkink`
157			`-- datapath and controller`
158			`-- Entity : radix4_multi_structure`
159			`-- Architecture : structural`
160			`-- Created on : 01/01/2004`
161
162			`library ieee;`
163
164			`use ieee.std_logic_1164.all;`
165			`use ieee.std_logic_unsigned.all;`
166
167			`b when 0, -- and, andi`
168			`a or b when 1, -- or, ori`
169			`a xor b when 2, -- eor`
170			`not a when 3; -- com`
171
172			`-- Shifter`
173			`right_out(6 downto 0) <= a(7 downto 1);`
174			`with rightsel select`
175			`right_out(7) <= '0' when 0, -- lsr`
176			`c_flag when 1, -- ror`
177			`a(7) when 2; -- asr`
178
179			`-- Direct Unit`
180			`with dirsel select`
181			`dir_out <= b when 0, -- ldi, mov`
182			`(a(3 downto 0) & a(7 downto 4)) when 1; -- swap`
183
184			`-- Bit Loader`
185			`process(bld, bitsel, a, t_flag, set)`
186			`begin`
187			`for i in 0 to 7 loop`
188			`if i /= bitsel then`
189			`bldcbi_out(i) <= a(i);`
190			`elsif bld = '1' then`
191			`bldcbi_out(i) <= t_flag;`
192			`else`
193			`bldcbi_out(i) <= set;`
194			`end if;`
195			`end loop;`
196			`end process;`
197
198			`-- Results to Data Bus`
199			`process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)`
200			`begin`
201
202			`c <= "ZZZZZZZZ";`
203
204			`-- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg`
205			`if add = '1' or subcp = '1' then`
206			`c <= sum;`
207			`end if;`
208
209			`-- and, andi, or, ori, eor, com`
210			`if logic = '1' then`
211			`c <= logic_out;`
212			`end if;`
213
214			`-- lsr, lsr, asr`
215			`if right = '1' then`
216			`c <= right_out;`
217			`end if;`
218
219			`-- ldi, mov, swap`
220			`if dir = '1' then`
221			`c <= dir_out;`
222			`end if;`
223
224			`-- bld, cbisbi`
225			`if bld = '1' or cbisbi = '1' then`
226			`c <= bldcbi_out;`
227			`end if;`
228
229			`-- out, st z, st z+, st -z`
230			`if pass_a = '1' then`
231			`c <= a;`
232			`end if;`
233
234			`end process;`
235
236
237			`-- Skip Evaluation Unit --`
238			`process(cpse, skiptest, a, b, set, bitsel, c)`
239			`begin`
240
241			`skip <= '0';`
242
243			`-- cpse`
244			`if cpse = '1' then`
245			`if a = b then`
246			`skip <= '1';`
247			`end if;`
248
249			`-- sbrc, sbrs`
250			`elsif skiptest = '1' then`
251			`if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then`
252			`skip <= '1';`
253			`end if;`
254
255			`end if;`
256			`end process;`
257
258			`-- Flags Evaluation Unit --`
259			`process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)`
260			`begin`
261
262			`-- C sr(0)`
263			`if add = '1' then`
264			`sr(0) <= cout;`
265			`elsif right = '1' then`
266			`sr(0) <= a(0);`
267			`elsif logic = '1' then -- com`
268			`sr(0) <= '1';`
269			`else -- subcp`
270			`sr(0) <= not cout;`
271			`--sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7));`
272			`end if;`
273
274			`-- Z sr(1)`
275			`if (add = '1' or subcp = '1') and sum = "00000000" then`
276			`sr(1) <= '1';`
277			`elsif logic = '1' and logic_out = "00000000" then`
278			`sr(1) <= '1';`
279			`elsif right = '1' and right_out = "00000000" then`
280			`sr(1) <= '1';`
281			`else`
282			`sr(1) <= '0';`
283			`end if;`
284
285			`-- N sr(2)`
286			`if (add = '1' or subcp = '1') and sum(7) = '1' then`
287			`sr(2) <= '1';`
288			`elsif logic = '1' and logic_out(7) = '1' then`
289			`sr(2) <= '1';`
290			`elsif right = '1' and right_out(7) = '1' then`
291			`sr(2) <= '1';`
292			`else`
293			`sr(2) <= '0';`
294			`end if;`
295
296			`-- V sr(3)`
297			`if right = '1' then`
298			`sr(3) <= right_out(7) xor a(0);`
299			`elsif logic = '1' then`
300			`sr(3) <= '0';`
301			`else`
302			`sr(3) <= overflow;`
303			`end if;`
304
305			`-- S sr(4)`
306			`sr(4) <= sr(2) xor sr(3);`
307
308			`-- H sr(5)`
309			`if add = '1' then`
310			`sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3));`
311			`else -- subcp`
312			`sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3));`
313			`end if;`
314
315			`-- T sr(6)`
316			`sr(6) <= a(bitsel);`
317
318			`end process;`
319
320			`tosr <= sr;`
321
322			`end alu;`
323
324
325