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[/] [ecpu_alu/] [trunk/] [alu/] [rtl/] [vhdl/] [alu_stimulus.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 5 leonous
    vector_stim_in : process ( clock_tb )
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                    variable i  : integer := 0;
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type out_vector is record
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      A           : std_logic_vector(8 downto 1)    ;
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      B           : std_logic_vector(8 downto 1)    ;
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      S           : std_logic_vector(4 downto 1)    ;
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      Y           : std_logic_vector(8 downto 1)    ;
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      CLR         : std_logic                       ;
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      CLK         : std_logic                       ;
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      C           : std_logic                       ;
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      V           : std_logic                       ;
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      Z           : std_logic                       ;
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 end record;
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type out_vectors is array (natural range <>) of out_vector;
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constant vectors  : out_vectors :=  (
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("UUUUUUUU", "UUUUUUUU", "UUUU", "UUUUUUUU", '1', '1', 'U', 'U', 'U'),
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("01010101", "00000001", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000010", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
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("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01011001", '0', '1', '0', '0', '0'),
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("01010101", "00001000", "0000", "01011001", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00010000", "0000", "01011101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00100000", "0000", "01100101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "01000000", "0000", "01110101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0000", "10010101", '0', '1', '0', '0', '0'),
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("01010101", "00000001", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0010", "11010101", '0', '1', '0', '0', '0'),
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("01010101", "00000010", "0010", "01010100", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0010", "01010011", '0', '1', '0', '0', '0'),
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("01010101", "00010000", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "01000000", "0010", "01010001", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0010", "01000101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
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("01010101", "00000001", "0100", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0100", "11010101", '0', '1', '0', '0', '0'),
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("01010101", "00000010", "0101", "10101010", '0', '1', '0', '0', '0'),
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("01010101", "00000000", "0101", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "00000100", "0100", "00010101", '0', '1', '0', '0', '0'),
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("01010101", "00010000", "0101", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "01000000", "0010", "01010000", '0', '1', '1', '0', '0'),
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("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
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("01010101", "10000000", "0010", "01010101", '0', '1', '0', '0', '0'));
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                 begin
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                    if (clock_tb'event and clock_tb = '1') then
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                        if ( i <= vectors'high) then
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                            A <= vectors(i).A;
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                            B <= vectors(i).B;
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                            S <= vectors(i).S;
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                            --Y <= vectors(i).Y;
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                            CLR <= vectors(i).CLR;
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                            CLK <= vectors(i).CLK;
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                            --C <= vectors(i).C;
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                            --V <= vectors(i).V;
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                            --Z <= vectors(i).Z;
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                            i := i + 1;
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                        else
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                            finished <= '1';
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                        end if;
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                    else
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                        CLK <= clock_tb;
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                    end if;
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                end process vector_stim_in;
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