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leonous |
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-- Module - Introduction to VLSI Design [03ELD005]
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-- Lecturer - Dr V. M. Dwyer
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-- Course - MEng Electronic and Electrical Engineering
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-- Year - Part D
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-- Student - Sahrfili Leonous Matturi A028459 [elslm]
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Final coursework 2004
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--
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-- Details: Design and Layout of an ALU
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Description : ALU testbench
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-- Entity : alu_tb
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-- Architecture : behavioural
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-- Created on : 07/03/2004
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all; -- for unsigned()
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use std.textio.all; -- for file i/o
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use work.txt_util.all; -- for string<->other types conversions
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entity alu_tb is
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end alu_tb;
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architecture behavioural of alu_tb is
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component alu
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port (
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A : in std_logic_vector(7 downto 0);
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B : in std_logic_vector(7 downto 0);
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S : in std_logic_vector(3 downto 0);
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Y : out std_logic_vector(7 downto 0);
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CLR : in std_logic ;
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CLK : in std_logic ;
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C : out std_logic ;
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V : out std_logic ;
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Z : out std_logic
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);
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end component;
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-- ALU test vector record
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type test_vector is record
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A : string(8 downto 1) ; -- ALU input operand 1
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B : string(8 downto 1) ; -- ALU input operand 2
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S : string(3 downto 1) ; -- ALU input opcode
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end record test_vector;
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-- records to store stimulus for verification
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signal this_record, next_record : test_vector;
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-- ALU access signals
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signal A : std_logic_vector(7 downto 0) ;
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signal B : std_logic_vector(7 downto 0) ;
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signal S : std_logic_vector(3 downto 0) ;
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signal Y : std_logic_vector(7 downto 0) ;
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signal CLR : std_logic ;
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signal CLK : std_logic ;
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signal C : std_logic ;
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signal V : std_logic ;
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signal Z : std_logic ;
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-- finished = '1' indicates end of test run
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signal finished : std_logic;
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-- used to synchronise verification with stimulus
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signal started : boolean := false;
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-- testbench clock half period
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constant CLK_HALF_PERIOD : time := 10 ns ;
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constant zero : std_logic_vector(7 downto 0)
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:= (others => '0');
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-- procedure to write a string to the screen
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procedure writestr (s : string) is
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variable lout : line;
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begin
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write(lout, s);
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writeline(output, lout);
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end writestr;
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-- procedure to write a character to the screen
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procedure writechr (s : character) is
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variable lout : line;
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begin
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write(lout, s);
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writeline(output, lout);
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end writechr;
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begin
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-- instantiate ALU
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alu_inst0 : alu
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port map (
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A ,
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B ,
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S ,
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Y ,
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CLR ,
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CLK ,
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C ,
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V ,
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Z
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);
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-- apply clock stimulus
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clock_stim : process
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begin
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CLK <= '1', '0' after CLK_HALF_PERIOD;
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if (finished /= '1') then
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wait for 2 * CLK_HALF_PERIOD;
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else
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wait; -- end test
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end if;
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end process clock_stim;
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apply_test_vectors
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: process
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-- uncomment this line for VHDL '87 file i/o
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--file infile : text is in "alu_test.txt";
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file infile : text open read_mode is "alu_test.txt";
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variable buff : line;
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variable in_vec : test_vector;
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variable aa, bb, yy
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: string(A'low + 1 to A'high + 1);
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variable ss, last_ss
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: string(1 to 3);
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variable cc, vv, zz, clrc, space
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: character;
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variable count : integer;
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-- function to return the opcode as a std_logic_vector
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-- from the given string
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function string2opcode(s: string) return std_logic_vector is
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variable opcode : std_logic_vector(3 downto 0);
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begin
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if (s = "add") then
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opcode := "0000";
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elsif (s = "inc") then
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opcode := "0001";
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elsif (s = "sub") then
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opcode := "0010";
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elsif (s = "cmp") then
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opcode := "0011";
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elsif (s = "and") then
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opcode := "1100";
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elsif (s = "or ") then
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opcode := "1101";
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elsif (s = "xor") then
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opcode := "1110";
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elsif (s = "cpl") then
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opcode := "1111";
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elsif (s = "asl") then
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opcode := "0100";
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elsif (s = "asr") then
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opcode := "0101";
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elsif (s = "clr") then
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opcode := "0110";
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end if;
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return opcode;
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end string2opcode;
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begin
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finished <= '0';
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count := 0;
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CLR <= '1';
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started <= false;
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while ( not endfile(infile) ) loop
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count := count + 1;
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-- verify outputs are as expected
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readline (infile, buff);
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if (count = 1) then
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readline (infile, buff); -- first read was the header
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writestr("**** Start of Test ****");
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end if;
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read (buff, aa);
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read (buff, space);
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read (buff, bb);
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read (buff, space);
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read (buff, ss);
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read (buff, space);
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read (buff, clrc);
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-- wait for falling edge of clk
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wait until (CLK'event and CLK = '0');
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-- wait for half of half a period
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wait for (CLK_HALF_PERIOD / 2);
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-- apply stimulus to inputs
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A <= to_std_logic_vector(aa);
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B <= to_std_logic_vector(bb);
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S <= string2opcode(ss);
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CLR <= to_std_logic(clrc);
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-- store stimulus for use when verifying outputs
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if (last_ss = "clr") then
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next_record.A <= str(zero);
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next_record.B <= str(zero);
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else
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next_record.A <= aa;
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next_record.B <= bb;
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end if;
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next_record.S <= ss;
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last_ss := ss;
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-- wait for rising edge of clock when data
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-- should be loaded from registers into ALU
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wait until clk'event and clk = '1';
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-- set local 'started' flag so verification can
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-- start
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-- grace period of 2 clock cycles for ALU to read
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-- first set of data
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if (clr = '0' and started = false) then
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wait until clk'event and clk = '1';
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wait until clk'event and clk = '1';
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started <= true;
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end if;
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end loop;
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-- end test
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finished <= '1';
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wait;
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end process apply_test_vectors;
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verify_test : process
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variable result : std_logic_vector(7 downto 0);
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variable op1, op2: std_logic_vector(7 downto 0);
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begin
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-- await positive clock edge
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wait until clk'event and clk = '1';
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-- wait a little more after results appear
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wait for (CLK_HALF_PERIOD/2);
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-- get expected record
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this_record <= next_record;
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if (started = true and clr = '0') then
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-- convert string operands from this_record
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-- into std_logic_vectors
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op1 := to_std_logic_vector(this_record.A);
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op2 := to_std_logic_vector(this_record.B);
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-- depending on opcode command string...perform
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-- high level equivalent of ALU operation and store
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-- in 'result'
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if (this_record.S = "add") then
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result := op1 + op2;
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elsif (this_record.S = "inc") then
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result := op1 + 1;
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elsif (this_record.S = "sub") then
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result := op1 - op2;
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elsif (this_record.S = "cmp") then
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result := y;
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elsif (this_record.S = "and") then
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result := op1 and op2;
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elsif (this_record.S = "or ") then
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result := op1 or op2;
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elsif (this_record.S = "xor") then
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result := op1 xor op2;
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elsif (this_record.S = "cpl") then
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result := not op2;
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-- VHDL functions sla and sra require left operand = bit_vector
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-- and right operand = integer
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-- bv2slv [see above] converts bit_vector to std_logic_vector
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elsif (this_record.S = "asl") then
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result := bv2slv(to_bitvector(op1) sla conv_integer(unsigned(op2 and x"07")));
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-- Also, these functions fill shifted bit positions with 1s not 0s
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-- so this has to be taken care of
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if (conv_integer(unsigned(op2 and x"07")) > 0) then
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result(conv_integer(unsigned(op2 and x"07")) - 1 downto 0) := (others => '0');
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end if;
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elsif (this_record.S = "asr") then
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result := bv2slv(to_bitvector(op1) sra conv_integer(unsigned(op2 and x"07")));
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if (conv_integer(unsigned(op2 and x"07")) > 1) then
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result(result'high - 1 downto result'high - conv_integer(unsigned(op2 and x"07")) + 1 ) := (others => '0');
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end if;
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elsif (this_record.S = "clr") then
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result := y;
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end if;
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writestr(hstr(to_std_logic_vector(this_record.A)) & " " & this_record.S & " " & hstr(to_std_logic_vector(this_record.B)) & " = " & hstr(Y) & " expected " & hstr(result));
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assert Y = result
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report "Output Y is wrong"
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severity warning;
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--assert C = to_std_logic(cc)
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-- report "Output C is wrong"
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-- severity warning;
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--assert V = to_std_logic(vv)
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-- report "Output V is wrong"
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-- severity warning;
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--assert Z = to_std_logic(zz)
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-- report "Output Z is wrong"
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-- severity warning;
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end if;
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end process verify_test;
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vector_stim_out : process ( A ,
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B ,
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S ,
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Y ,
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CLR ,
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CLK ,
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C ,
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V ,
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Z
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)
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| 316 |
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-- type out_vector is record
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-- A : string(8 downto 0) ;
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-- B : string(8 downto 0) ;
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-- S : string(4 downto 0) ;
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-- Y : string(8 downto 0) ;
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-- CLR : string(1 downto 1) ;
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-- CLK : string(1 downto 1) ;
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-- C : string(1 downto 1) ;
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-- V : string(1 downto 1) ;
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-- Z : string(1 downto 1) ;
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-- end record;
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file infile : text open write_mode is "alu_test.out";
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variable buff : line ;
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| 329 |
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constant space : string := " ";
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| 330 |
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begin
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| 331 |
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if (CLK'event) then
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| 332 |
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write (buff, str(A));
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write (buff, space);
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| 334 |
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write (buff, str(B));
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| 335 |
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write (buff, space);
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| 336 |
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write (buff, str(S));
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| 337 |
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write (buff, space);
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| 338 |
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write (buff, str(Y));
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| 339 |
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write (buff, space);
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| 340 |
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write (buff, str(CLR));
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| 341 |
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write (buff, space);
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| 342 |
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write (buff, str(CLK));
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| 343 |
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write (buff, space);
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| 344 |
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write (buff, str(C));
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| 345 |
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write (buff, space);
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| 346 |
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write (buff, str(V));
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| 347 |
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write (buff, space);
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| 348 |
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write (buff, str(Z));
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| 349 |
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writeline (infile, buff);
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| 350 |
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end if;
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| 351 |
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|
|
| 352 |
|
|
end process vector_stim_out;
|
| 353 |
|
|
end behavioural;
|
| 354 |
|
|
|
