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https://opencores.org/ocsvn/ecpu_alu/ecpu_alu/trunk
[/] [ecpu_alu/] [trunk/] [alu/] [synth/] [veriwell.log] - Blame information for rev 5
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leonous |
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Veriwell version 2.8.7,
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Copyright (C) 1993-2008 Elliot Mednick and Mark Hummel
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Veriwell comes with ABSOLUTELY NO WARRANTY; This is free
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software, and you are welcome to redistribute it under the
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terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License,
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or (at your option) any later version.
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lxt support compiled in
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lxt2 support compiled in
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Entering Phase I...
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Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/..//barrel_shifter/simple/barrel_shifter_simple.v
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Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/..//adder/alu_adder.v
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Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_datapath.v
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Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_controller.v
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Compiling included source file '/home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_controller.vh'
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Continuing compilation of source file '/home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu_controller.v'
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Compiling source file : /home/leonous/projects/verilog/ecpu/components/alu/rtl/verilog/alu.v
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Entering Phase II...
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Entering Phase III...
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No errors in compilation
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Top-level modules:
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alu
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Normal exit
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Thank you for using Veriwell
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