URL https://opencores.org/ocsvn/ecpu_alu/ecpu_alu/trunk

Subversion Repositories ecpu_alu

[/] [ecpu_alu/] [trunk/] [alu/] [systemc/] [obj_dir/] [verilog_sc.h] - Blame information for rev 5

Details | Compare with Previous | View Log


#include <cstdlib>
class verilog_sc {
public:
    // CONSTRUCTORS
    verilog_sc() {}
    ~verilog_sc() {}
    // METHODS
    // This function will be called from a instance created in Verilog
    inline uint32_t randomit() {
     return random() % (1 << 16);
    }
};

Line No.	Rev	Author	Line
1	5	leonous	`#include <cstdlib>`
2			`class verilog_sc {`
3			`public:`
4			`// CONSTRUCTORS`
5			`verilog_sc() {}`
6			`~verilog_sc() {}`
7			`// METHODS`
8			`// This function will be called from a instance created in Verilog`
9			`inline uint32_t randomit() {`
10			`return random() % (1 << 16);`
11			`}`
12			`};`

Browse

Tools

Subversion Repositories ecpu_alu

[/] [ecpu_alu/] [trunk/] [alu/] [systemc/] [obj_dir/] [verilog_sc.h] - Blame information for rev 5